Abstract: A structure for high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices, is disclosed. The present invention includes a semiconductor substrate and at least two dielectric regions in the substrate, one of the dielectric regions being spaced from the other of the dielectric regions by a channel region. The structure also includes at least two drift regions, each of the drift regions being adjacent to and in contact with each of the dielectric regions respectively. A gate region is formed on the substrate, wherein the gate region covers the channel region and portions of the dielectric regions. A source region adjacent to one of the dielectric region is formed, wherein the source region is spaced from the channel region by such adjacent dielectric region.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said layer of dielectric material and between said source/drain regions. The method further comprises forming a gate dielectric above said layer of polysilicon and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a layer of dielectric material, a plurality of source/drain regions positioned above the layer of dielectric material, and a layer of polysilicon positioned above said layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above said layer of polysilicon and a gate conductor positioned above said gate dielectric.

Abstract: A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.

Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.

Abstract: A multi-purpose device that can serve as either a resistor, MOSFET or JFET is disclosed. The resistor is formed by selecting a first metal interconnect configuration, the MOSFET is formed by selecting a second metal interconnect configuration, and the JFET is formed by selecting a third metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array that uses resistors may be increased. In addition, and because no special processing is typically required, the device may be desirable for use in other types of structures such as standard cells and custom logic.

Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.

Abstract: A SOI device, comprising: a SOI wafer having a stack structure of a silicon substrate, a buried oxide layer having a first and a second contact holes and a silicon layer; an isolation layer formed in the silicon layer to define a device formation region; a transistor including a gate formed over the device formation region of the silicon layer defined by the isolation layer, source and drain regions formed at the both side of the gate in the device formation region, and a channel region which is a portion of the device formation region between the source and drain region; a conduction layer being contacted with the buried oxide layer; an impurity region for well pick-up formed in the silicon layer to be contacted with the buried oxide layer; a first contact layer formed within the first contact hole of the buried oxide layer to electrically connect the channel region of the transistor and the conduction layer; and a second contact layer formed with the second contact hole of the buried oxide layer to electri

Abstract: A thin film semiconductor device includes a glass supporting body having thereon an insulating substrate which is attached thereto by a layer of adhesive material. On the surface of the substrate facing the supporting body is a layer of semiconductor material which includes therein a semiconductor element, such surface further having thereon a metalization pattern of conductor tracks. An insulating layer is additionally provided between the metalization pattern and the adhesive layer, and has a dielectric constant &egr;r below 3 and a thickness in the range of approximately 20 &mgr;m to 60 &mgr;m. By virtue of such additional layer, parasitic capacitanees between the metalization pattern and an envelope in which the device is included or a printed circuit board on which the device is mounted are reduced substantially, thereby reducing the power consumption of the device.

Abstract: Electromigration in the source and drain conductors of a semiconductor device is reduced by increasing the cross-sectional areas of these conductors in accordance with an increase in a magnitude of current, thereby enabling the semiconductor device to operate at high temperatures.

Abstract: A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

Abstract: A display device having high definition and high reliability, and technology for manufacturing the same. In an active matrix type display device of integrated peripheral driving circuit type, pixel TFTs of an active matrix circuit 100 are not provided with LDD regions. Also, among circuits constituting peripheral driving circuits 101, 102, buffer circuits, of which a high withstand voltage and high-speed operation are required, are made with thin film transistors having floating island regions and base regions between source and drain regions of their active layers.

Abstract: According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground.

Abstract: The present invention provides a source/drain structure formed in a semiconductor layer which has source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions. The body portion is positioned under a gate insulation film over which a gate electrode is provided. The source region has a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region. For the first present invention, it is important that a distance of an inside edge portion of the first low resistive region from a first interface between the source region and the body portion is shorter than a distance of an inside portion of the second low resistive region from a second interface between the drain region and the body portion.

Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

Abstract: A method of manufacturing a semiconductor device for preventing ESD damage is disclosed. A semiconductor device for preventing against ESD damage according to a first embodiment of the present invention, is fabricated as follows. Firstly, first impurity ions of a first conductivity type are implanted into a first region of a substrate of a semiconductor device using a first ion implantation, to form a first impurity ion layer. Here, a junction region will be formed in the first region and is connected to an input pad. Second impurity ions of the first conductivity type are then implanted into a second region of the substrate using a second ion implantation, to form a second impurity ion layer over the first ion impurity ion layer. Here, the second region includes the first region. Next, third impurity ions of a second conductivity type are implanted into the substrate of both sides of the first and second impurity ion layers, using a third ion implantation, to form a third impurity ion layer.

Abstract: A high performance pixel is described for active matrix electronic displays. The pixel combines a compact, mesa-isolated PMOS access transistor with a novel, area-efficient HV device. The high voltage transistor features a P+ region at each end of the source to effectively eliminate the parasitic sidewall component and raise the nominal threshold voltage. Concurrently, excess well area is eliminated from the PMOS access transistor to minimize device leakage and the undesirable capacitance component. The improved design enhances pixel response, increases operating margins and contrast and may reduce power dissipation in the off-state.

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: A thin film transistor includes a substrate, a gate electrode, an insulating film, a semiconductor film, a source electrode, a drain electrode, wherein in at least one electrode of the gate electrode, the source electrode and the drain electrode, end portion of the at least one electrode is tapered in such a manner that a thickness decreases in a direction toward end face of the at least one electrode, the at least one electrode being composed of one electrode material, and prescribed physical property of the at least one electrode being changed in a direction perpendicular to a surface of the at least one electrode, so that an etching rate of the at least one electrode is changed in the direction.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate.

Abstract: A liquid crystal display has wires made of aluminum alloy layer, and two molybdenum-tungsten alloy layers MoW located on/under the aluminum alloy layer, respectively. To form a wire, the first molybdenum-tungsten alloy layer, the aluminum alloy layer, and the second molybdenum-tungsten alloy layer are sequentially deposited. The molybdenum-tungsten alloy layer has different etch rates for one etchant, depending on the deposition temperature and tungsten content ratio. Particularly, since the molybdenum-tungsten alloy layer has an etch rate similar to that of an aluminum layer and aluminum alloy layer for an aluminum etchant CH.sub.3 COOH/HNO.sub.3 /H.sub.3 PO.sub.4 /H.sub.2 O.

Abstract: A semiconductor device includes: a substrate; a line formed on the substrate; and a crystalline semiconductor film containing silicon connected to the line. The crystalline semiconductor film is crystallized by annealing where a constituting material of the line functions as a catalyst.

Abstract: The present invention relates in general to power ICs, etc. having the SOI structure, and more specifically to the structure in which an SOI substrate comprises a base substrate, an SOI oxide film formed on the base substrate, and active layers formed on the SOI oxide film, and also integrates on itself power devices and the corresponding control elements monolithically. Between this base substrate and this SOI oxide film is formed heavily-doped semiconductor regions having a conductivity type opposite to that of this base substrate. Hence, the junction capacitance between the base substrate and the heavily-doped semiconductor regions decreases an actual capacitance between the base substrate and the active layer so that to inhibit or prevent inversion layers from being formed at the bottom of the active layers.

Abstract: A stacked semiconductor structure is designed for component arrangement of an IC (integrated circuit) device having a large number of various types of junction devices, such as diodes, well resistors, N.sup.+ resistors, and BJTs (bipolar junction transistors) and MOS (metal-oxide semiconductor) transistors. The stacked semiconductor structure is constructed on an SOI (silicon-on-insulator) structure which includes a semiconductor substrate; a buried insulator layer formed over the substrate; and a silicon film formed over the buried insulator layer. Based on this SOI structure, the various types of junction devices are arranged in the substrate beneath the buried insulator layer; while the MOS transistors are arranged in the silicon film above the buried insulator layer, with the silicon film further being further formed with a plurality of trenches for isolating the MOS transistors from each other.

Abstract: An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably N atoms, within a gate dielectric/silicon-based substrate interfacial region using gas cluster ion beam implantation. Gas cluster ion beam implantation involves supercooling a gas to form clusters of atoms from the molecules in the gas. Those clusters of atoms are then ionized and accelerated to a target. Upon striking the target, the clusters of atoms break up into individual atoms. The energy of the ionized cluster is uniformly distributed to the individual atoms. As such, the atoms have a relatively low energy, and thus may be implanted to a shallow depth of less than 100 .ANG.. Barrier atoms positioned within a gate dielectric/substrate interfacial region serve to inhibit the diffusion of metal atoms and impurities from an overlying gate conductor into the substrate. Furthermore, the barrier layer provides protection against hot carrier injection into and entrapment within the gate dielectric.

Abstract: A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: A thin film field effect transistor includes source and drain regions, an active region sandwiched by the source and drain semiconductor regions. A gate insulating film is provided to cover the source and drain regions and the active region, and a semiconductor gate is formed on the gate insulating film above the active region. A gate electrode is formed on the semiconductor gate such that a non-covering portion where the gate electrode does not cover the semiconductor gate is formed.

Abstract: The invention is concerned with the fabrication of a MIS semiconductor device of high reliability by using a low-temperature process. Disclosed is a method of fabricating a MIS semiconductor device, wherein doped regions are selectively formed in a semiconductor substrate or a semiconductor thin film, provisions are then made so that laser or equivalent high-intensity light is radiated also onto the boundaries between the doped regions and their adjacent active region, and the laser or equivalent high-intensity light is radiated from above to accomplish activation.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A silicon-on-insulator metallic oxide semiconductor structure having a double implanted source region. By etching a trench contact window in the double implanted source region and then depositing a metal into the trench to form a metal plug, contact between the source terminal and the substrate is established. Consequently, floating body effect of a silicon-on-insulator device is prevented without having to provide additional surface area to accommodate the contact window.

Abstract: In an active matrix electroluminescent display, a pixel containing a electroluminescent cell and the switching electronics for the electroluminescent cell where said switching electronics contains two transistors, a low voltage MOS transistor and a high voltage MOS transistor. A low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. The gate charge is stored between the gate electrode of the high voltage transistor and an electric field shield forming a pixel signal capacitor. The pixel signal capacitor is positioned within the layout of the pixel a distance from the drain of the high voltage MOS transistor.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10.sup.10 Ohms-um divided by the width of the pass-gate.

Abstract: An SOI semiconductor substrate and a fabrication method therefor which are capable of preventing a depletion region due to a fixed electric charge occurring at a junction surface from being formed in a silicon wafer within which an integrated circuit is to be formed. The SOI semiconductor substrate includes a first silicon wafer, a first oxide layer formed on an upper surface of the first silicon wafer, an undoped polysilicon layer formed on an upper surface of the first oxide layer, and a second silicon wafer formed on an upper surface of the polysilicon layer.

Abstract: Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g.

Abstract: Semiconductor devices such as thin-film transistors formed by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a dielectric layer (24) to provide electrical isolation. The semiconductor device (10) includes a drain extension region (101) that extend from a drain region (44) to a gate structure (20). The semiconductor device (10) also has a conductive structure (105) that is adjacent to the gate structure (20).

Abstract: A liquid crystal display (LCD) includes silicide-preventing regions between an amorphous silicon layer and source and drain regions. The silicide-preventing regions, which may be thin oxide regions, act as silicide barriers without degrading the contact resistance characteristics. The doped amorphous silicon layer and the amorphous layer may then be uniformly etched by reducing and preferably preventing the formation of silicide when forming the source and drain electrodes.

Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is "gettered" into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.

Abstract: On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions are included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.

Abstract: A thin film transistor (10) in an electronic device such as an active matrix display panel having an intrinsic amorphous silicon semiconductor layer (22) providing a channel region (23) between source and drain electrodes (14, 16) includes directly adjacent to the side of the semiconductor layer (22) remote from the gate electrode (25) at the channel region (23) a layer (20) of amorphous semiconductor material which has a high defect density and low conductivity that serves to provide recombination centres for photogenerated carriers. Leakage problems due to the photoconductive properties of the intrinsic semiconductor material are then reduced. Conveniently, an hydrogenated silicon rich amorphous silicon alloy (e.g. nitride etc) can be used for the recombination centre layer (20).

Abstract: A semiconductor device comprises a composite substrate comprising a semiconductor substrate and a semiconductor layer on said semiconductor substrate with a dielectric layer interposed therebetween; a plurality of element regions formed in the semiconductor layer and each having formed a field effect transistor including a source region and a drain region of a first conduction type; and an impurity-diffused region of a second conduction type which is formed directly under an element isolating film isolating respective elements. The impurity-diffused region having the opposite conduction type and formed under the element separating film restrain formation of parasitic transistors and prevent a decrease in threshold value.

Abstract: In a semiconductor device including a full depletion MISFET transistor made by using a SOI layer and intended to stabilize a predetermined threshold value while holding the threshold value sensitivity to fluctuation in thickness of the SOI layer even upon changes in impurity concentration of a channel region of the MISFET transistor by changing a back gate voltage in accordance with the impurity concentration of the channel region, thickness of the SOI layer is determined to reduce changes in threshold value, and impurity concentration of the channel region is measured by using a detector element to adjust the back gate voltage in response to the measured value. Thus, the desired threshold voltage can be maintained.

Abstract: A high voltage device. A first-type semiconductor substrate having at least a gate formed thereon is provided. The high voltage comprises a second-type first diffusion region in the semiconductor region, a second-type second diffusion region within the first diffusion region, a second-type third diffusion region under the second diffusion region, a field oxide layer on a part of the second diffusion region, and a first-type source/drain region under a surface between the field oxide layer and the gate.

Abstract: A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions.

Abstract: A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.

Abstract: A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral MOS device on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and over at least a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.