Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.

Abstract: A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor.

Abstract: The electrostatic protective device includes an insulator and a semiconductor layer. The semiconductor layer includes a device forming region and a device separating region. The device forming region includes a primary first conductive impurity diffused layer, a body region, a secondary first conductive impurity diffused layer, and a second conductive region that are arranged in order. The second conductive region includes a second conductive impurity diffused layer separated electrically from the body region. The device separating region includes a device separating layer that surrounds the device forming region. A gate electrode is further provided on the body region in the semiconductor layer with an insulating film interposed in between.

Abstract: A pixel structure is disclosed. The pixel structure includes first transparent conductive films that are arranged on color-resists of a color filter substrate, and second transparent conductive films that are arranged on sub pixel regions of an array substrate and correspond to the first transparent conductive films. The first transparent conductive films are connected with one another. An area of an orthographic projection of each first transparent conductive film on a corresponding second transparent conductive film is equal to an area of the second transparent conductive film. According to the present disclosure, the pixel structure has a higher light transmittance.

Abstract: A method of manufacturing a thin film transistor is provided, and includes: providing a substrate; depositing a buffer layer and patterning the buffer layer; sequentially depositing an insulation layer and a first metal layer, coating a photoresist on the first metal layer; metal etching the first metal layer; ashing the photoresist; metal etching the first metal layer of the lightly doped region; implanting ions to an active area; and removing the photoresist.

Abstract: An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.

Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.

Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.

Abstract: A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.

Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.

Abstract: An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.

Abstract: An array substrate, a display panel and a method of manufacturing array substrate are provided. The array substrate, comprising first substrate and data line, data line positioned on first substrate; auxiliary electrode positioned on first substrate, auxiliary electrode for electrically connecting to color filter, vertical projection of auxiliary electrode on first substrate does not intersect with data line; insulating layer positioned on surface of auxiliary electrode which away first substrate, insulating layer has hole; and shielding electrode comprises main section and protrusion section are integrated, main section is located on lateral side of data line which away first substrate, and vertical projection of main section on first substrate is covering data line, protrusion section is positioned on insulating layer, and protrusion section pass through hole and contacting to auxiliary electrode. It achieves to highly product yield and saving production costs.

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.

Abstract: A device includes an integrated circuit (IC) layer, an insulative layer such as a buried oxide (BOX) layer, a substrate layer separated from the IC layer by the insulative layer, and a set of protective components such as a set of Zener diodes or a Zener stack coupled to the IC layer to protect the IC layer from transient electric events such as an electrostatic discharge (ESD), an inductive flyback, and a back electromotive force (back-EMF) event. The Zener stack has a Zener breakdown voltage greater than a breakdown voltage of the IC layer. An effective bias voltage has a voltage level less than the breakdown voltage of the IC layer. The Zener diode or Zener stack may be coupled to one or more isolation structures of the IC layer. The isolation structures separate the IC layer into electrically distinct portions or wells in which other electric components are formed.

Abstract: An organic light emitting diode (OELD) driver for driving at least one OELD having a transition time. The OLED driver has a power supply coupled to a bias pulse controller and an injection pulse controller. The bias pulse controller is configured to generate a bias pulse output based on the OLED transition time. The injection pulse controller is configured to generate an injection pulse output. A combiner is coupled to the bias pulse output and the injection pulse output. The combiner is configured to generate a combined output to drive the OLED. A system controller may be coupled to at least one of the power supply, bias pulse controller and injection pulse controller to adjust the voltage/current delivered to the OLED to adjust a light level output of the OLED. The OLED driver may include a switch that changes a dwell time of the bias pulse controller output.

Abstract: A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.

Abstract: A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.

Abstract: Even when a light shielding film is provided between a transistor and a substrate, a threshold voltage of the transistor can be prevented or suppressed from being shifted. A display device includes light shielding films provided between a substrate and a semiconductor layer of a transistor including a gate electrode and the semiconductor layer. The semiconductor layer includes a source region and a drain region. Both of the light shielding films overlap the semiconductor layer when seen in a plan view, and are spaced apart from each other in a direction.

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

Abstract: A production method for a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed such that a portion of the modified layer in terms of a thickness direction becomes an amorphous layer and an average depth of an amorphous layer surface at a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.

Abstract: An array substrate is disclosed. The array substrate includes: a substrate adopting an organic material; an isolation layer adopting a metal material, and the isolation layer is formed on the substrate; and a buffering layer formed at a side of the isolation layer away from the substrate. In the array substrate of the present invention, in a high-temperature PECVD process, a pollution problem caused by the plasma directly bombarding the substrate made of an organic material can be avoid. A display device applying the array substrate and a manufacturing method for an array substrate are also disclosed.

Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates stacked pair(s) of field effect transistors (FETs), where each stacked pair has a shared gate. The structure also includes an irregular-shaped buried interconnect that connects source/drain regions that are on opposite sides of the shared gate and at different levels (i.e., a lower FET's source/drain region on one side of the shared gate to an upper FET's source/drain region on the opposite side). Also disclosed is a method for forming the structure by forming, during different process stages, different sections of an irregular-shaped cavity (including sections that expose surfaces of the source/drain regions at issue and a section with sidewalls lined by a dielectric spacer) and filling the different sections with sacrificial material. When all of the sections are completed, the sacrificial material is selectively removed, thereby creating the irregular-shaped cavity. Then, the buried interconnect is formed within the cavity.

Abstract: Disclosed is a radio frequency (RF) switch that includes a substrate and a plurality of elongated drain/source (D/S) diffusion regions laterally disposed in parallel with one another and separated by a plurality of elongated channel regions. A plurality of elongated D/S resistor regions extends between an adjacent pair of plurality of elongated D/S diffusion regions, and a plurality of elongated gate structures resides over corresponding ones of the elongated channel regions. A silicide layer resides over a majority of at least top surfaces of the plurality of the elongated D/S diffusion regions and the plurality of elongated gate structures, wherein less than a majority of each of the plurality of the elongated D/S resistor regions are covered by the silicide layer.

Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.

Abstract: A display device is provided. The display device includes a first base substrate, a gate line on the first base substrate and extending in a first direction, a data line disposed on the first base substrate, insulated from the gate line, and extending in a second direction, which crosses the first direction, a switch on the first base substrate and electrically connected to the gate line and the data line, an insulating layer on the switch, a first electrode on the insulating layer, a light-shielding conductive layer directly contacting the first electrode and overlapping the switch, and a second electrode insulated from the first electrode and the light-shielding conductive layer, at least partially overlapping the first electrode, and electrically connected to the switch.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOT substrate is included.

Abstract: The present application discloses a light emitting diode packaging structure comprising a base substrate; a metal lead on the base substrate; a cover plate; and a seal frame sealing the cover plate and the base substrate together and forming an enclosure surrounding a display area of the base substrate. The metal lead extends from the display area outwardly and passes through below the seal frame to outside of the enclosure. The metal lead has a curved configuration in plan view of the base substrate within a region where the metal lead overlaps with the seal frame.

Abstract: A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.

Abstract: A display device includes a display panel, a panel driver, panel-side output terminals, image signal lines, and control signal lines. The terminals are disposed in a non-display area of the display device and connected to the panel driver. The image signal lines are routed in the non-display area from the terminals to cross a long edge of the panel driver and spread in a fan-like form toward the display area. The control signal lines including first lines and second lines are routed in the non-display area from the terminals toward a display area of the display device. The first lines are routed from the terminals to cross the long edge and along the image signal lines toward the display area. The second lines each including portions having a width larger than the first lines are routed from the terminals to cross a short edge of the panel driver.

Abstract: The gate electrode is provided on the gate insulating film. The interlayer insulating film is provided to cover the gate electrode. The interlayer insulating film includes a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms, a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms. The second insulating film has a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface. The third insulating film is in contact with at least one of the second surface and the third surface.

Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.

Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.

Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.

Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.

Abstract: Provided are a semiconductor device and a fabricating method thereof.

Abstract: This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (TFT) characteristics. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. The p-type metal oxide films may be hydrogenated such that they have a hydrogen content of at least 1018 atoms/cm3, and in some implementations, at least 1020 atoms/cm3, or higher. Examples of hydrogenated p-type metal oxide films include hydrogenated tin (II)-based films and hydrogenated copper (I)-based films. The TFTs may be characterized by having one or more TFT characteristics such as high mobility, low subthreshold swing (s-value), and high on/off current ratio.

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.