Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

Abstract: A thin-film dielectric having a higher dielectric constant than usual ones and not requiring a special single crystal substrate, and a large-capacity thin-film capacitor element using the thin-film dielectric, in which a BaTiO3-based perovskite solid solution and a KNbO3-based perovskite solid solution are alternately formed to form a crystal structure gradient region where a lattice constant continuously changes at the interface, and thus crystal lattice strain occurs, thereby permitting the production of a thin-film dielectric having a high dielectric constant; also, a large-capacity thin-film capacitor element can be produced by using the thin-film dielectric of the present invention.

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.

Abstract: Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

Abstract: Semiconductor structures and methods for forming the same are provided. The method for forming a semiconductor structure includes forming an N-well region in a substrate and forming a first protection layer over the N-well region. The method for forming a semiconductor structure further includes forming a P-well region in the substrate and forming a second protection layer over the P-well region. The method for forming a semiconductor structure further includes growing a first channel layer over the first protection layer and a second channel layer over the second protection layer and forming a first gate structure over the first channel layer and a second gate structure over the second channel layer.

Abstract: In a pixel including a selection transistor, a driver transistor, and a light-emitting element, as the driver transistor, a transistor is used in which a channel is formed in an oxide semiconductor film and its channel length is 0.5 ?m or greater and 4.5 ?m or less. The driver transistor includes a first gate electrode over an oxide semiconductor film and a second gate electrode below the oxide semiconductor film. The first gate electrode and the second gate electrode are electrically connected to each other and overlap with the oxide semiconductor film. Furthermore, in the selection transistor of a pixel, which does not need to have field-effect mobility as high as that of the driver transistor, a channel length is made longer than at least the channel length of the driver transistor.

Abstract: A display panel includes a substrate. A scan line and a data line intersect with each other and are disposed on the substrate. An active layer is disposed on the substrate and between the data line and the substrate. A transparent conductive layer is disposed on the substrate and above the active layer. The active layer includes a contact region electrically connected to the data line, a second contact region electrically connected to the transparent conductive layer, and an intermediate region disposed between the first and the second contact regions. A portion of the intermediate region overlapping with the scan line is a channel region. A portion of the intermediate region not overlapping with the scan line is a non-channel region. The width of the non-channel region is greater than the width of the channel region.

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

Abstract: A display device includes an output circuit including a differential amplifier circuit, an output amplifier circuit that includes a first transistor of the first conduction type coupled between the first supply terminal and the output terminal, and including a control terminal coupled to the differential amplifier circuit, a first control circuit, an input terminal, an output terminal, and first to third supply terminals to which first to third supply voltages are applied, wherein the third supply voltage is set to a voltage between the first supply voltage and the second supply voltage, or the second supply voltage, and wherein the first control circuit includes a third transistor and a first switch which are coupled in series between the first supply terminal and the control terminal of the first transistor.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

Abstract: A liquid crystal display (“LCD”) device capable of easily setting up an accurate resistance ratio between thin film transistors, the LCD device includes a first substrate including a gate line and a data line, a second substrate opposing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first sub-pixel electrode in a first sub-pixel region of the first substrate, a second sub-pixel electrode in a second sub-pixel region of the first substrate, a first transistor connected to the gate line, the data line, and the first sub-pixel electrode, a second transistor connected to the gate line, the first transistor, and the second sub-pixel electrode, and a third transistor connected to the gate line, the second sub-pixel electrode, and a storage line, wherein one of the first, second, and third transistors includes a plurality of divided channel regions.

Abstract: The present disclosure provides an organic light-emitting display apparatus and a fabrication method thereof. The organic light-emitting display apparatus comprises a substrate having a device component layer; first electrodes disposed over the device component layer; a pixel-defining layer having opening regions to expose the first electrodes formed over the device component layer; photo spacers, disposed on the pixel-defining layer, and surrounding at least one opening region to provide a first photo spacer group along the at least one opening region in a first direction and provide a second photo spacer group along the at least one opening region in a second direction; an organic light-emitting layer disposed in the opening regions of the pixel-defining layer and in contact with the first electrodes; and a second electrode disposed on the light-emitting layer.

Abstract: A TFT array substrate which includes a plurality of pixels arranged in a matrix, has each pixel including sub-pixels in a 2×2 matrix. Two data lines are between neighboring columns of the sub-pixels and scan line is arranged between neighboring rows of the sub-pixels. The sub-pixels in same row can be electrically coupled to one scan line. The sub-pixels for the same color in one same column can be electrically coupled to the neighboring data line. The sub-pixels configured to display another same color in the same column can be electrically coupled to another neighboring same data line. Each two adjacent sub-pixels displaying a same color have opposite polarities.

Abstract: The present invention is directed to a light emitting device structured so as to increase the amount of light which is taken out in a certain direction after emitted from a light emitting element, and a method of manufacturing this light emitting device. An upper end portion of an insulating material 19 that covers an end portion of a first electrode 18 is formed to have a curved surface having a radius of curvature, a second electrode 23a is formed to have a slant face as going from its center portion toward its end portion along the curved surface. Light emitted from a light emitting layer comprising an organic material 20 that is formed on the second electrode 23a is reflected at the slant face of the second electrode 23a to increase the total amount of light taken out in the direction indicated by the arrow in FIG. 1A.

Abstract: A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor including a first gate electrode, a second gate electrode, a third gate electrode, a first oxide semiconductor channel layer, a second oxide semiconductor channel layer, and two source/drain electrodes. The second gate electrode is disposed above the first gate electrode. The third gate electrode is disposed above the second gate electrode. At least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode. At least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode. At least a part of each source/drain electrode is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer. Each source/drain electrode contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer.

Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Abstract: An organic light emitting display device includes a substrate having a display area and a non-display area, an organic light emitting element and a sealing layer sequentially stacked on one side of the substrate in the display area, a support layer on the one side of the substrate in the non-display area, and a polarizing plate on the support layer in the non-display area and on the sealing layer in the display area, the polarizing plate covering an entirety of the support layer.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Abstract: A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a channel layer in the drift layer; a second impurity layer in the channel layer; a separation insulation film on the drift layer between the channel layer and the first impurity layer; a gate insulation film on a channel region between the second impurity layer and the drift layer connected with the separation insulation film; a gate electrode on the gate insulation film and the separation insulation film; a first electrode connected with the first impurity layer; a second electrode connected with the second impurity layer and the channel layer; and a field plate on the separation insulation film between the gate electrode and the first electrode and connected with the first electrode. The field plate is larger than the gate electrode in a current direction.

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

Abstract: A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

Abstract: A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.

Abstract: An organic light-emitting device includes at least one functional layer for generating electroluminescent radiation, an encapsulation structure formed on or over the at least one functional layer, and a heat conduction layer formed on or over the encapsulation structure. The heat conduction layer includes a matrix material and heat conducting particles embedded in the matrix material.

Abstract: A display device includes two or more pixels disposed in a pixel area in which two or more data lines intersect two or more gate lines; a common electrode commonly disposed on the pixels; a first gate high voltage supplied through a first gate voltage line, a portion of the first gate high voltage overlapping the common electrode; a second gate high voltage supplied through a second gate voltage line, a portion of the second gate high voltage overlapping the common electrode; a connecting line structure in contact with the common electrode, and extending from the common electrode in a direction toward a position in which the common electrode does not overlap the first gate voltage line.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.

Abstract: A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

Abstract: A patterned photoresist having an overlay tolerance of (x+y)/2 is formed over preselected hard mask portions or semiconductor fin portions, wherein x is a width of a semiconductor fin and y is a distance between a neighboring pair of semiconductor fins. Hard mask portions or semiconductor fin portions not protected by the patterned photoresist are then removed by an isotropic etching process. The patterned photoresist is removed. In some embodiments, the remaining hard mask portions are employed as fin forming etch masks.

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.

Abstract: A method for fabricating an integrated circuit that include providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate, dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and one or both of a medium voltage FET region and a high voltage FET regions, and forming a low voltage FET within the low voltage FET regions and forming a medium and/or high voltage FET within the medium and/or high voltage FET region(s). Channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer that is disposed above a buried oxide layer of the ETSOI substrate, whereas channel, source, and drain structures of the medium and/or high voltage FETs are formed at least partially below the upper silicon layer.

Abstract: A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor.

Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Abstract: An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the insulation layer and electrically connected to a scan line, a protection layer covering the gate electrode, a source electrode and a drain electrode electrically connected to a source region and a drain region of the semiconductor layer. A channel region is disposed between the source region and the drain region. A source lightly doped region is disposed between the channel region and the source region. A drain lightly doped region is disposed between the channel region and the drain region. The light shielding pattern shields the source region, the drain region, the source lightly doped region and the drain lightly doped region. The light shielding pattern is overlapped with one side of the scan line and not overlapped with another side of the scan line.

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.