Abstract: The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.

Abstract: A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.

Abstract: Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: The present invention comprises a first main face (22a) on the surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered onto the first main face (22a). The semiconductor chip (29), etc. are sealed in a hollow space made by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the glass plate (36) are adhered by the light-shielding adhesive resin made of epoxy resin. Accordingly, there can be provided the semiconductor device and a method of manufacturing the same, which can prevent the direct incidence of the light onto the semiconductor chip (29) and the degradation of the characteristic of the semiconductor chip (29) can be suppressed.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

Abstract: The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract: A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.

Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.

Abstract: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts and electrical interconnection leads may also be substantially transparent. Methods for making and using such double-injection field-effect transistors are also disclosed.

Abstract: When a SOI substrate is produced a first silicon layer epitaxially grown on the insulating underlay is ion implanted to make deep part of interface of the silicon layer amorphous, and then annealed to recrystallize. Next, the silicon layer is heat treated to oxidize part of the surface side, and after the silicon oxide is removed by etching, a silicon layer is epitaxially grown on the remaining first silicon layer to form a second silicon layer. Subsequently, the second silicon layer is again ion implanted to make deep part of interface amorphous, then annealing is performed to recrystallize. With this method, a SOI substrate, which is very small in crystal defect density of the silicon layer and good in surface flatness, can be produced. Therefore, on the semiconductor substrate an electronic device or optical device having high device performance and reliability can be realized.

Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).

Abstract: In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

Abstract: A III nitride buffer film including at least Al element and having a screw-type dislocation density of 1×108/cm2 or less is formed on a base made from a sapphire single crystal, etc., to fabricate an epitaxial base substrate. Then, a III nitride underfilm is formed on the III nitride buffer film, to fabricate an epitaxial substrate.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

Abstract: The present invention provides a semiconductor device comprising a single-crystal silicon substrate; and a single-crystal oxide thin film having a perovskite structure formed through epitaxial growth on the single-crystal silicon substrate. The single-crystal oxide thin film is directly in contact with a surface of the single-crystal silicon substrate, and contains a bivalent metal that is reactive to silicon.

Abstract: This invention is intended to provide a technique for improving characteristics of a TFT and realizing a structure of the TFT optimum for driving conditions of a pixel section and a driving circuit by using a small number of photomasks. The TFT includes a first electrode, a first insulating film put between a semiconductor film and the first electrode, a second electrode, and a second insulating film put between the semiconductor film and the second electrode. The first electrode and the second electrode are overlapped with each other, with a channel formation region of the semiconductor film put between the first electrode and the second electrode, and a constant voltage is always applied to the first electrode.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.

Abstract: A nitride-based semiconductor element capable of effectively preventing a nitride-based semiconductor layer of a first area from cracking and reducing the degree of warpage of a substrate is obtained. This nitride-based semiconductor element comprises a first region formed on a prescribed region of a substrate and provided with an element including a first nitride-based semiconductor layer having a prescribed thickness and a second region formed on a region of the substrate other than the first region and provided with the first nitride-based semiconductor layer with a thickness smaller than the thickness in the first region. Thus, strain easily concentrates to the second region provided with the first nitride-based semiconductor layer with the smaller thickness, whereby strain of the first region provided with the element is relaxed.

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: A display device comprising a substrate having an insulating surface; a first signal line extending over said substrate; a first bottom gate type thin film transistor having a channel region comprising crystalline silicon formed over said substrate wherein a gate of said first thin film transistor is connected to said first signal line; a second signal line extending across said first signal line; a second bottom gate type thin film transistor having a channel region comprising crystalline silicon formed over said substrate wherein agate of said second thin film transistor is electrically connected to said second signal line through at least said first thin film transistor; a voltage supply line formed over said substrate; a pixel electrode formed over said substrate wherein the pixel electrode is connected to said voltage supply line through at least said second thin film transistor.

Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short-channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.

Abstract: A semiconductor substrate, for forming a circuit pattern of a semiconductor chip, comprised of a substrate, an insulating film formed on the substrate, and a semiconductor layer formed on the insulating film, wherein the semiconductor layer is isolated by the insulating film for every region formed with a circuit pattern of a semiconductor chip, able to be generally used even if a silicon on insulator or semiconductor on insulator (SOI) layer is isolated by an insulating film, and a process of production of an SOI substrate, enabling a reduction of thickness of the SOI layer and able to suppress the manufacturing costs and variation in the thickness of the SOI layer, comprising forming a groove in a first substrate made of a semiconductor, forming a first insulating film in the groove and on the first substrate, injecting hydrogen ions to form a peeling layer, bonding a second substrate, peeling off the first substrate by heat treatment while leaving the semiconductor layer, and polishing the semiconductor la

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: A retaining substrate for mounting a semiconductor element thereon, having a circuit pattern for said semiconductor element, characterized in that said substrate comprises an insulative material, said substrate has a surface configuration having a cross section comprising (a) an uneven shaped portion and (b) a concave shaped portion which are arranged in tandem wherein a surface of said uneven shaped portion (a) makes a bottom face of said concave portion (b), and said uneven shaped portion (a) has a structure in that (a-i) an insulative convex shaped portion and (a-ii) an insulative concave shaped portion are alternately arranged so as to neighbor with each other, and said circuit pattern is provided in said concave shaped portion (a-ii) of said uneven shaped portion (a).

Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.

Abstract: A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

Abstract: A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills the trench and forms a filler plug. The gate layers adjacent to the trench are then patterned and etched and the filler plug is removed to obtain gate stacks spaced apart by a distance of less than about 400 Angstroms.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: In forming a pair of impurity regions in an active layer, an intrinsic or substantially intrinsic region having a double-sided comb shape is also formed by using a proper mask. The intrinsic or substantially intrinsic region is composed of a portion that effectively functions as a channel forming region and portions in which a channel is not formed and which function as heat sinks. The heat dissipation effect is improved because the heat sinks are formed by the same material as the channel forming region.

Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.

Abstract: An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Abstract: Silicon and silicon-germanium semiconductor-on-insulator structures are formed with strong bonds between the silicon or silicon-germanium layer and the underlying insulating substrate with low defects in the semiconductor and minimal flaws in the bonding between the semiconductor layer and the substrate. An oxide layer is initially formed on the semiconductor wafer, and the wafer may then be annealed, if necessary, to drive off water from the oxide layer so that the oxide layer is well below the water saturation of the oxide. The surfaces of the oxide layer and the substrate are then cleaned and placed into contact at relatively low temperatures to effect a strong bond. The semiconductor layer may then be thinned by mechanical or chemical processes, or both, and the completed structure annealed to perfect the bond between the semiconductor layer and the substrate.

Abstract: A doped area is formed in the silicon substrate layer of a silicon-on-insulator stack including a silicon substrate, an insulator layer and an silicon active layer, by implanting a species through at least the insulator layer. In one embodiment, the silicon active layer is etched and the species are implanted in the silicon substrate through the exposed insulator layer. Thus, a doped region is formed in the silicon substrate under the areas where the silicon active layer was removed. In another embodiment after etching the silicon active layer, a dielectric layer is formed adjacent to the silicon active layer and on the insulator layer. In this embodiment, the species are implanted over the entire wafer through both the silicon active layer and the insulator layer. In both embodiments, the species are implanted before forming a gate electrode of a transistor.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: This invention provides a transparent Cu—Al—O semi-conducting film having a p-type conductivity greater than 0.95×10−1 S·cm−1. This invention also relates to a process for preparing a Cu—Al—O film having p-type conductivity, comprising: a) controllably vaporizing organo-copper and organo-aluminum precursors and carrying the vapors into a chemical vapor deposition chamber with an inert gas flow; b)reacting and depositing the vapors on a substrate, preferably a light-transmitting substrate, through a chemical vapor deposition process.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with an impurity to increase free carrier conductivity. The source region and the drain region are heavily doped with the impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and each are fabricated of a metal with an energy gap greater than silicon to form Schottky junctions with the channel region.

Abstract: A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.

Abstract: A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

Abstract: A CMOS device and a method for fabricating the same, is disclosed, the device including an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second epitaxial semiconductor layers formed on the first and second sapphire patterns, isolating structures formed at edges of the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacer structures formed at both sides of the first and second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film, first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impur