Single Crystal Islands Of Semiconductor Layer Containing Only One Active Device Patents (Class 257/353)
  • Patent number: 11031505
    Abstract: A transistor carried by a substrate comprising an active layer, the transistor comprising: at least one source area and at least one drain area; at least one electrical contact area; at least one conduction channel; at least one gate; wherein the gate comprises: a longitudinal portion; a transverse portion extending on either side of a portion of the active layer and comprising: at least a first portion extending beyond a portion of a first side of the portion of the active layer on a first extension dimension I2; at least a second portion extending beyond a portion of a second side of the portion of the active layer on a second extension dimension I3; and in that: I2>I3 with I3?0.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 8, 2021
    Assignee: X-FAB FRANCE
    Inventors: Philippe Trovati, Nicolas Pons, Pascal Costaganna, Francis Domart
  • Patent number: 10950721
    Abstract: Certain aspects of the present disclosure generally relate to a transistor having a self-aligned drift region and asymmetric spacers. One example transistor generally includes a channel region; a gate region disposed above the channel region; a first implant region; a second implant region having a same doping type as the first implant region, but a different doping type than the channel region; a first spacer disposed adjacent to a first side of the gate region; a second spacer disposed adjacent to a second side of the gate region and having a wider width than the first spacer; and a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region. The channel region may be disposed between the first implant region and the drift region.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Ranadeep Dutta
  • Patent number: 10923602
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Patent number: 10868125
    Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 15, 2020
    Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
  • Patent number: 10845627
    Abstract: A meta device may include: a substrate; a mirror disposed on the substrate; a refractive index modulation layer disposed on the mirror; a nanoantenna facing the mirror with the refractive index modulation layer, the refractive index modulation layer being disposed between the nanoantenna and the mirror; and an insulating layer disposed between the nanoantenna and the refractive index modulation layer and having a non-uniform thickness. Since the thickness of the insulating layer is not uniform, a withstanding voltage characteristic of the meta device is improved.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunil Kim, Changbum Lee, Byounglyong Choi
  • Patent number: 10803226
    Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Do, Jong-Hoon Jung, Seung-Young Lee, Tae-Joong Song
  • Patent number: 10784143
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang, Yue Zhong
  • Patent number: 10727289
    Abstract: The present disclosure provides a manufacturing method of an array substrate, including: forming a gate layer on a substrate; forming a gate insulating material layer on the gate layer; forming a polysilicon material layer on the gate insulating material layer; depositing an etch stop material layer on the polysilicon material layer; channel doping the polysilicon material layer; etching the polysilicon material layer, the etch stop material layer and the gate insulating material layer to form an active layer, an etch stop layer and a gate insulating layer; forming a source/drain layer on the active layer and the gate insulating layer, the active layer being electrically connected to the source/drain layer; and forming a through hole on the source/drain layer to form a source and a drain, the through hole being corresponding to the active layer, and both of the source and the drain being electrically connected to the active layer.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 28, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Sihang Bai
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10707328
    Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li
  • Patent number: 10692976
    Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 23, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jenn Hwa Huang, Weixiao Huang
  • Patent number: 10665702
    Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung Gil Kang, Ill Seo Kang, Yong Hee Park, Sang Hoon Baek, Keon Yong Cheon
  • Patent number: 10651257
    Abstract: The present disclosure provides a manufacturing method of an array substrate, including: forming a gate layer on a substrate; forming a gate insulating material layer on the gate layer; forming a polysilicon material layer on the gate insulating material layer; depositing an etch stop material layer on the polysilicon material layer; channel doping the polysilicon material layer; etching the polysilicon material layer, the etch stop material layer and the gate insulating material layer to form an active layer, an etch stop layer and a gate insulating layer; forming a source/drain layer on the active layer and the gate insulating layer, the active layer being electrically connected to the source/drain layer, and forming a through hole on the source/drain layer to form a source and a drain, the through hole being corresponding to the active layer, and both of the source and the drain being electrically connected to the active layer.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 12, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Sihang Bai
  • Patent number: 10615278
    Abstract: A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung
  • Patent number: 10510870
    Abstract: A method for forming a semiconductor device may include providing a transistor structure. The transistor structure may include a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures. The method may include implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins. The altered portion of the isolation layer may have a first etch rate, wherein an unaltered portion of the isolation layer, not exposed to the ions, has a second etch rate, greater than the first etch rate.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: December 17, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Sony Varghese, Jae Young Lee, Johannes Van Meer
  • Patent number: 10418454
    Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTL. (SHANGHAI) CORP., SEMICONDUCTOR MANUFACTURING INTL. (BEIJING) CORP.
    Inventors: Yong Li, Zhongshan Hong
  • Patent number: 10403752
    Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Chandra S. Mohapatra, Anand S. Murthy, Stephen M. Cea, Tahir Ghani
  • Patent number: 10347766
    Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Shuo Ho, Chia-Ming Chang, Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien
  • Patent number: 10304929
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 10304961
    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shuhei Nagatsuka, Yutaka Shionoiri
  • Patent number: 10297686
    Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10170372
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • Patent number: 10164092
    Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10164072
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10153280
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Patent number: 10079239
    Abstract: A compact three-dimensional mask-programmed read-only memory (3D-MPROMC) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 18, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10062782
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10043770
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Patent number: 9986641
    Abstract: A circuit board includes a laminated body including a laminate of a plurality of insulating-material layers made of a flexible material. External electrodes are provided on the top surface of the laminated body. An electronic component is mounted on the external electrodes. A plurality of internal conductors, when viewed in plan in the z-axis direction, are overlaid on the external electrodes and are not connected to one another in regions in which the internal conductors are overlaid on the external electrodes.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: May 29, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Noboru Kato
  • Patent number: 9978849
    Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 22, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
  • Patent number: 9935092
    Abstract: A RF transistor stack is described. The RF transistor stack comprises a first transistor having a T-gate layout configuration. The first transistor has a body region; a plurality of drain regions; and a plurality of source regions. A second transistor is provided which has a T-gate layout configuration. The second transistor has a body region; a plurality of drain regions; and a plurality of source regions. An interconnect operably couples the source regions of the first transistor with the source regions of the second transistor such that the distortion due to asymmetry in the division of RF voltage between the drain to source and the source to body terminals of first transistor is cancelled by reversing the asymmetry in the division of the RF voltage in the second transistor.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 3, 2018
    Assignee: Ferfics Limited
    Inventors: John Anthony O'Sullivan, John Keane
  • Patent number: 9881919
    Abstract: A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9876108
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 9859420
    Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9853151
    Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Tenko Yamashita
  • Patent number: 9768296
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 19, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitava Chatterjee
  • Patent number: 9689835
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Shao Liu, Rashid Bashir, Fei-Lung Lai, Chun-wen Cheng
  • Patent number: 9670534
    Abstract: Disclosed herein are methods for array assembly and detection. The methods can use an incubation chamber containing a suspension of nucleic acid targets, polymerase and a set of oligonucleotide probes bound to magnetic beads in a randomly dispersed state. Each probe can have a target binding domain that is complementary to a target nucleic acid, a closing domain with a sequence that is complementary to the sequence of the target binding domain, and a joining region between the binding domain and the closing domain, which is not complementary to the target nucleic acid. Method steps can include providing the incubation chamber, placing the incubation chamber in a magnetic trap, generating a magnetic field that induces the magnetic beads to migrate towards a substrate and, once in proximity to the substrate, to interact with each other repulsively and reorganize into arrays, and imaging the array.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: June 6, 2017
    Assignee: BioArray Solutions, Ltd.
    Inventors: Michael Seul, Yi Zhang, Sukanta Banerjee, Jiacheng Yang, Chiu Chau
  • Patent number: 9666602
    Abstract: A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Seon Lee, Dong-Jo Kim, Yoon-Ho Khang, Yong-Su Lee, Jong-Chan Lee
  • Patent number: 9666722
    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shuhei Nagatsuka, Yutaka Shionoiri
  • Patent number: 9647129
    Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Ryota Hodo, Shinya Sasagawa, Yuki Hata
  • Patent number: 9559091
    Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.
    Type: Grant
    Filed: June 21, 2015
    Date of Patent: January 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9559159
    Abstract: A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S3) on a substrate (S1) by a patterning process, in which the a-Si layer (S3) comprises a plurality of convex structures (S32) and etched areas (S31) which are disposed along circumference of the plurality of convex structures and partially etched; and performing excimer laser crystallization (ELC) on the a-Si layer (S3) and obtaining the LTPS membrane. A thin-film transistor (TFT) and a display device are further disclosed, which are used for overcoming poor uniformity of the polysilicon membrane prepared by the ELC technology.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 31, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Huijuan Zhang
  • Patent number: 9496397
    Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9455246
    Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9425257
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a channel layer formed of a Germanium compound having a Germanium concentration B formed on a semiconductor substrate having a Germanium concentration of A, the Germanium concentration of the substrate A being less than the Germanium concentration of the channel layer B. The structure further includes a capping layer formed to separate the channel layer from a metal gate, the capping layer having a Germanium concentration of C, the Germanium concentration of the channel layer B being greater than the Germanium concentration of the capping layer C.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Ka-Hing Fung
  • Patent number: 9368515
    Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Jo Kim, Ji Seon Lee, Jong Chan Lee, Yoon Ho Khang, Sang Ho Park, Yong Su Lee, Jung Kyu Lee
  • Patent number: 9349866
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a fin structure disposed over a substrate. The fin structure includes a semiconductor oxide layer disposed over the substrate, which has a top surface facing away from the substrate, a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, which has a top surface facing away from the substrate and an opposing bottom surface facing the substrate, and a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer. The device also includes a gate dielectric layer disposed over the fin structure and a gate electrode layer disposed over the gate dielectric layer. The gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Cheng Ching
  • Patent number: 9331064
    Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9305883
    Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis