Including Means To Eliminate Island Edge Effects (e.g., Insulating Filling Between Islands, Or Ions In Island Edges) Patents (Class 257/354)
  • Patent number: 10243039
    Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 26, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld, Reza Ghandi
  • Patent number: 10103136
    Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • Patent number: 10037988
    Abstract: A method of forming a HV lateral PNP BJT with a pulled back isolation structure and a polysilicon gate covering a part of the NW+HVNDDD base region and a part of the collector extension (HVPDDD) and the resulting device are provided. Embodiments include forming a DVNWELL in a portion of a p-sub; forming a HVPDDD in a portion of the DVNWELL; forming a LVPW in a portion of the HVPDDD; forming a first and a second NW laterally separated in a portion of the DVNWELL, the first and second NW being laterally separated from the HVPDDD; forming a N+ base, a P+ emitter, and a P+ collector in an upper portion of the first and second NW and LVPW, respectively; forming a STI structure between the P+ emitter and P+ collector in a portion of the DVNWELL, HVPDDD, and LVPW, respectively; and forming a SAB layer over the STI structure.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Rudy Octavius Sihombing, Tsung-Che Tsai, Chai Ean Gill
  • Patent number: 9958918
    Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Patent number: 9953837
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Caubet, Sylvain Baudot
  • Patent number: 9911841
    Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 6, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Barraud, Ivan Duchemin, Louis Hutin, Yann-Michel Niquet, Maud Vinet
  • Patent number: 9472380
    Abstract: The present invention relates to a silicon part and a method of producing the silicon part. The silicon part is not worn quickly and particle formation is suppressed even if it is positioned in the reaction chamber of a plasma etching apparatus. The silicon part for the plasma etching apparatus is made of any one selected from a group consisting of poly-crystalline silicon, mono-like silicon, and single-crystalline silicon. Also, the silicon part includes boron as a dopant in a range from 1×1018 atoms/cc or higher to 1×1020 atoms/cc or lower.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: October 18, 2016
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Fumitake Kikuchi, Yoshinobu Nakada
  • Patent number: 9443966
    Abstract: An n-type region encloses an n-type well region is disclosed in which is disposed a high-side drive circuit. A high resistance polysilicon thin film configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n-type region. An OUT electrode, a ground electrode, and a Vcc1 electrode are disposed on the n-type region. The Vcc1 electrode is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor). The OUT electrode is connected to the negative electrode of the auxiliary direct current power supply. One end portion (a second contact portion) of the high resistance polysilicon thin film is connected to the ground electrode, and the other end portion (a first contact portion) of the high resistance polysilicon thin film is connected to the OUT electrode.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: September 13, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 9337651
    Abstract: An electrostatic discharge (ESD) protection circuit includes a first n-type transistor, a discharge acceleration circuit and a discharge time circuit. The first n-type transistor has a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad. The discharge acceleration circuit is coupled to the gate of the first n-type transistor to the I/O pad during the ESD event and coupled to the gate of the first n-type transistor to the reference voltage when there is no ESD event. The discharge time circuit, coupled to the discharge acceleration circuit and the supply voltage, controls a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: May 10, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 9324843
    Abstract: Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, John Bruley, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 9304346
    Abstract: A display device includes: a first substrate and a second substrate which are located so that inner main surfaces thereof face each other; a liquid crystal layer located between the first substrate and the second substrate; a seal material located between the first substrate and the second substrate so as to surround the liquid crystal layer, the seal material bonding the first substrate and the second substrate to each other; an organic insulation film located in a seal formation area on the inner main surface of the second substrate, the organic insulation film having an opening section in the seal formation area; and an inorganic insulation film located to continue from an inside of the opening section to a surface of the organic insulation film through an inner wall surface of the opening section, the inorganic insulation film being directly covered with the seal material.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: April 5, 2016
    Assignee: Kyocera Corporation
    Inventors: Teruhiko Ichimura, Hideaki Sakai, Shigeki Kitamura, Hiroaki Ito
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 8951896
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • Patent number: 8941214
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventor: Bernhard Sell
  • Patent number: 8872225
    Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 28, 2014
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van Le, Robert Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy Zelick
  • Patent number: 8836131
    Abstract: A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Peter Kanschat, Indrajit Paul
  • Patent number: 8729609
    Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 20, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Frank Scott Johnson, Andreas Knorr
  • Patent number: 8723262
    Abstract: FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Huiming Bu, Effendi Leobandung, Theodorus E. Standaert, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8716800
    Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 6, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo, Qingqing Liang
  • Patent number: 8703557
    Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: April 22, 2014
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Xiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8674471
    Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 18, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomohide Terashima
  • Patent number: 8624321
    Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Hiromichi Godo, Hidekazu Miyairi
  • Patent number: 8624320
    Abstract: An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: January 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 8587062
    Abstract: A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Haining S. Yang
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Patent number: 8507989
    Abstract: An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: August 13, 2013
    Assignee: International Business Machine Corporation
    Inventors: Ali Khakifirooz, Kangguo Cheng, Bruce B. Doris
  • Patent number: 8502317
    Abstract: A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption.
    Type: Grant
    Filed: February 7, 2010
    Date of Patent: August 6, 2013
    Inventors: Leendert Jan van den Berg, Duncan George Elliott
  • Patent number: 8426920
    Abstract: The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 8390026
    Abstract: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Ted R. White
  • Patent number: 8389995
    Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
  • Patent number: 8288248
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8273629
    Abstract: The present invention, provides a semiconductor device including a substrate including a semiconductor layer overlying an insulating layer, wherein a back gate structure is present underlying the insulating layer and a front gate structure on the semiconductor layer; a channel dopant region underlying the front gate structure of the substrate, wherein the channel dopant region has a first concentration present at an interface of the semiconductor layer and the insulating layer and at least a second concentration present at the interface of the front gate structure and the semiconductor layer, wherein the first concentration is greater than the second concentration; and a source region and drain region present in the semiconductor layer of the substrate.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Paul C. Parries
  • Patent number: 8188564
    Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: May 29, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa
  • Patent number: 8188543
    Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 29, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
  • Patent number: 8169027
    Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: May 1, 2012
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta
  • Patent number: 8134207
    Abstract: In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 ?m or more.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: March 13, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Atsuo Watanabe
  • Patent number: 8124975
    Abstract: Provided is a display device capable of suppressing generation of optical leakage current as well as increase in capacitance in a case where a plurality of thin film transistors (TFTs) including a gate electrode film on a light source side are formed in series. Relative areas of opposing regions between a semiconductor film and the gate electrode film with respect to channel regions are different in at least a part of the plurality of TFTs, to thereby provide a flat panel display having a structure for suppressing increase in capacitance while suppressing generation of optical leakage current.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 28, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takeshi Noda, Toshio Miyazawa, Takuo Kaitoh, Hiroyuki Abe
  • Patent number: 8115254
    Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
  • Patent number: 8102000
    Abstract: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: January 24, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Zoran Krivokapic
  • Patent number: 8044465
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: October 25, 2011
    Assignee: S.O.I.TEC Solicon On Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Patent number: 8013364
    Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
  • Patent number: 8013327
    Abstract: A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 6, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kawasaki, Masaaki Fujimori, Takeo Shiba, Shuji Imazeki, Tadashi Arai
  • Patent number: 7994574
    Abstract: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO2 is 1.5. The thick portion of the silicon layer provides a core and the insulation films corresponding to this thick portion provide clads, thereby forming an optical waveguide along the predetermined path. The silicon layer at the side of the surface has a uniform thickness, thereby enabling characteristics of MOS devices fabricated on various portions of the silicon layer to be met with each other easily and facilitating a design of the electrical device as a whole.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 9, 2011
    Assignee: Sony Corporation
    Inventor: Koichiro Kishima
  • Patent number: 7943933
    Abstract: Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The thin film transistor substrate has a substrate, a semiconductor layer and source-drain electrodes. The source-drain electrodes are composed of oxygen-containing layers and thin films of pure copper or a copper alloy. The oxygen-containing layer contains oxygen such that part or all of oxygen combines with silicon in the semiconductor layer. And, the thin films of pure copper or a copper alloy connect with the semiconductor layer of the thin film transistor through the oxygen-containing layers.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: May 17, 2011
    Assignee: Kobe Steel, Ltd.
    Inventors: Aya Hino, Hiroshi Gotou
  • Patent number: 7939395
    Abstract: Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lillian Kamal, legal representative, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Yun Shi, William R. Tonti
  • Patent number: 7928510
    Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Ryosuke Watanabe
  • Patent number: 7916230
    Abstract: A pixel unit of TFT-LCD array substrate and a manufacturing method thereof is disclosed. In the manufacturing method, besides a first insulating layer and a passivation layer, a second insulating layer is adopted to cover the gate island, and forms an opening on the gate island to expose the channel region, the source region and the drain region of the TFT. A gray tone mask and a photoresist lifting-off process are utilized to perform patterning, so that the TFT-LCD array substrate can be achieved with just three masks.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: March 29, 2011
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Haijun Qiu, Zhangtao Wang, Xu Chen, Tae Yup Min
  • Patent number: 7906813
    Abstract: A semiconductor device, includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconductor substrate, isolated from each other by the first circuit block.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: March 15, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7880233
    Abstract: Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: February 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong Ho Park
  • Patent number: 7863621
    Abstract: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on the polycrystalline silicon layer.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: January 4, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park