Abstract: According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground.

Abstract: A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

Abstract: The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate insulating layer is formed of a filtering oxide layer having a thickness of 1 to 20 ?.

Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric layer can overlie the recess-resistant layer. A semiconductor layer overlying the buried insulator stack. Active devices, such as transistors and diodes, can be formed in the semiconductor layer.

Abstract: Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.

Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.

Abstract: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.

Abstract: A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.

Abstract: An individual identifier is easily provided in a semiconductor device capable of wireless communication. The semiconductor device includes a thin film transistor including a channel forming region, an island-like semiconductor film including a source region and a drain region, a gate insulating film, and a gate electrode; an interlayer insulating film; a plurality of contact holes formed in the interlayer insulating film which reach one of the source region and the drain region; and a single contact hole which reaches the other of the source region and the drain region, wherein a diameter of the single contact hole is larger than a diameter of each of the plurality of contact holes, and a sum of areas of bases of the plurality of contact holes is equal to an area of a base of the single contact hole.

Abstract: A method of manufacturing a thin film transistor is disclosed. The method includes forming an amorphous silicon layer and a blocking layer on an insulating substrate, forming a photoresist layer having first and second photoresist patterns on the blocking layer, etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns, reflowing the photoresist layer, forming a metal layer over the entire surface of the insulating substrate, removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer, crystallizing the amorphous silicon layer to form a poly silicon layer having a MILC front, etching the polysilicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers and to remove the MILC front, and removing the first and second blocking patterns.

Abstract: This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films provided on both side surfaces of the floating body region; gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; and a source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.

Abstract: A semiconductor device includes a substrate with an insulating surface and a single crystal semiconductor layer, which is bonded to the insulating surface of the substrate. The device further includes a first insulating layer, which is provided between the insulating surface of the substrate and the single crystal semiconductor layer, and a second insulating layer, which has been deposited on the entire insulating surface of the substrate except an area in which the first insulating layer is present.

Abstract: A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well region provided in the support substrate under the MOSFET.

Abstract: A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.

Abstract: A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block.

Abstract: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.

Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.

Abstract: A semiconductor device comprising a high breakdown voltage transistor and a low breakdown voltage transistor. The semiconductor device comprises a support substrate, an insulating layer formed on the support substrate, a high breakdown voltage transistor, a low breakdown voltage transistor, wherein the high breakdown voltage transistor is adjacent to a first isolation region having a depth that reaches the insulating layer, and the low breakdown voltage transistor is adjacent to a second isolation region having a depth that does not reach the insulating layer.

Abstract: A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the transistor, and the top plate of the capacitor.

Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

Abstract: A semiconductor device includes a semiconductor layer formed on a semiconductor substrate via an insulating film and having a projecting shape, a gate electrode formed, via a gate insulating film, on a pair of side surfaces of four side surfaces of the semiconductor layer and a source region and drain region formed on two side surfaces, on which the gate electrode is not formed, of the four side surfaces of the semiconductor layer. A portion of a channel region formed in the semiconductor layer is electrically connected to the gate electrode.

Abstract: A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.

Abstract: A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insulator, and has at least one MOSFET element. The MOSFET element includes a source region; a drain region which is opposed to the source region; a body region disposed between the source and drain regions; a gate region positioned on or close to a surface of the body region, so as to form an electrically conducting channel in the body region; and an extracting region being in contact with both of the body region and the source region. The extracting region has a conductivity type which is the same as a conductivity type of the body region and has a concentration higher than that of the body region.

Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.

Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: An active matrix display device using a thin film transistor as a switching element in the displaying portion or driving portion is characterized in that said thin film transistor includes an insulating substrate on which a gate electrode, a gate insulating film, a semiconductor layer, a drain electrode, a source electrode and a passivation film are successively laminated. The thin film transistor is further characterized such that the surface portion of the semiconductor layer on the side of the passivation film is porous, which enables the device to be stably driven with a low off-current even in the case of disposing an organic passivation film and a picture element electrode on the thin film transistor.

Abstract: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.

Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: A silicon-on-insulator (SOI) substrate includes a silicon substrate including an active region defined by a field region that surrounds the active region for device isolation. The field region includes a first oxygen-ion-injected isolation region and a second oxygen-ion-injected isolation region. The first oxygen-ion-injected isolation region has a first thickness and is disposed under the active region, a center of the first oxygen-ion-injected isolation region being at a first depth from a top surface of the silicon substrate. The second oxygen-ion-injected isolation region has a second thickness that is greater than the first thickness, the second oxygen-ion-injected isolation region disposed at sides of the active region and formed from a ton surface of the silicon substrate, a center of the second oxygen-ion-injected region disposed at a second depth from the top surface of the silicon substrate.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the transistor gate.

Abstract: A semiconductor device includes a semiconductor layer provided on a semiconductor substrate with an insulating film interposed therebetween. A gate electrode is provided on the semiconductor layer with a gate insulating film interposed therebetween, and a pair of source/drain regions are formed in the semiconductor layer so as to hold a body region under the gate electrode therebetween. A control section supplies voltages to the source/drain regions. The control section supplies the body region in an OFF state and ON state with a first voltage and a second voltage different from the first voltage, respectively. The second voltage is set such that a potential of the body region in the OFF state is substantially the same as a potential of the body region in the ON state.

Abstract: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.

Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

Abstract: The present invention is for providing a sophisticated active matrix type organic semiconductor device. A first electrode 102 is formed on an insulated surface. A second insulated film 104 is formed on the first electrode 102 via a first insulated film 103. An organic semiconductor film is formed on an opening part formed on the second insulated film 104 and the second insulated film 104. An organic semiconductor film 105 is obtained by polishing the same until the second insulated film 104 is exposed. Furthermore, by forming a second electrode 106 and a third electrode 107 on the organic semiconductor film 105, an organic semiconductor device of the present invention can be obtained.

Abstract: A first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor are formed using a plurality of single crystal grains, the plurality of single crystal grains being formed substantially centered on each of a plurality of starting-point portions disposed on an insulating surface of a substrate, the plurality of single crystal grains being composed of at least a first single crystal grain and a second single crystal grain adjacent to each other, with a crystal grain boundary therebetween, the first-conductivity-type thin film transistor includes at least a first-conductivity-type drain region formed adjacent to the crystal grain boundary in the first single crystal grain, the second-conductivity-type thin film transistor includes at least a second-conductivity-type drain region formed adjacent to the crystal grain boundary in the second single crystal grain, and a common electrode is provided on the crystal grain boundary to lead out outputs from the first-conductivity-type dra

Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.

Abstract: An epitaxial semiconductor wafer having a wafer substrate made of semiconductor single crystal, an epitaxial layer deposited on a top surface of said wafer substrate and a polysilicon layer deposited on a back surface of said wafer substrate. The semiconductor single crystal is exposed in a region defined within a distance of at least 50 ?m from a ridge line as a center, which is defined as an intersection line between said back surface and a bevel face interconnecting said top surface and said back surface of said wafer substrate. The polysilicon layer is 1.0 to 2.0 ?m thick. The epitaxial layer is 1.0 to 20 ?m thick. The wafer substrate is a silicon single crystal.

Abstract: A semiconductor device includes a substrate, a semiconductor layer of a first conductivity type having a single-crystal structure, and a plurality of transistors each including a first gate electrode provided above the semiconductor layer with a first gate insulation film laid therebetween, a pair of impurity regions of a second conductivity type being provided in the semiconductor layer and each becoming a source or drain region, and a channel body of the first conductivity type provided in the semiconductor layer at a portion between these impurity regions.

Abstract: A method of producing a top gate thin-film transistor comprises the steps of forming doped silicon source and drain regions (6a,8a) on an insulating substrate (2) and subjecting the face of the substrate (2) on which the source and drain regions (6a,8a) are formed to plasma treatment to form a doped surface layer. An amorphous silicon layer (12) is formed on the doped surface layer over at least the spacing between the source and drain regions (6a,8a) and an insulated gate structure (14,16) is formed over the amorphous silicon layer (12). Laser annealing of areas of the amorphous silicon layer not shielded by the gate conductor is carried out to form polysilicon portions (12a,12b) having the impurities diffused therein. In the method of the invention, doped silicon source and drain regions underlie the silicon layer to be crystallized using the laser annealing process. It has been found that the laser annealing process can then result in crystallization of the full thickness of the amorphous silicon layer.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.