In Complementary Field Effect Transistor Integrated Circuit Patents (Class 257/357)
-
Publication number: 20070284665Abstract: According to an embodiment of the present invention, an electrostatic discharge protection circuit used for a semiconductor device including a first power supply terminal, a second power supply terminal, and an input/output terminal, includes: a thyristor passing a surge current from the input/output terminal to the second power supply terminal; and a bipolar transistor passing a surge current from the first power supply terminal to the input/output terminal.Type: ApplicationFiled: June 5, 2007Publication date: December 13, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Takayuki Nagai
-
Patent number: 7298008Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.Type: GrantFiled: January 20, 2006Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A. Mousa, Christopher Stephen Putnam
-
Patent number: 7298009Abstract: A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.Type: GrantFiled: February 1, 2005Date of Patent: November 20, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Jiang Yan, Chun-Yung Sung, Danny Pak-Chum Shum, Alois Gutmann
-
Patent number: 7298010Abstract: A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.Type: GrantFiled: February 21, 2006Date of Patent: November 20, 2007Assignee: Sandia CorporationInventor: Kwok K. Ma
-
Patent number: 7294935Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.Type: GrantFiled: January 24, 2001Date of Patent: November 13, 2007Assignee: HRL Laboratories, LLCInventors: Lap-Wai Chow, James P. Baukus, William M. Clark, Jr.
-
Patent number: 7288822Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.Type: GrantFiled: April 7, 2006Date of Patent: October 30, 2007Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
-
Patent number: 7288789Abstract: A semiconductor device in which TFTs of suitable structures are arranged depending upon the performances of the circuits, and storage capacitors are formed occupying small areas, the semiconductor device featuring high performance and bright image. The thickness of the gate-insulating film is differed depending upon a circuit that gives importance to the operation speed and a circuit that gives importance to the gate-insulating breakdown voltage, and the position for forming the LDD region is differed depending upon the TFT that gives importance to the countermeasure against the hot carriers and the TFT that gives importance to the countermeasure against the off current. This makes it possible to realize a semiconductor device of high performance. Further, the storage capacity is formed by a light-shielding film and an oxide thereof to minimize its area, and a semiconductor device capable of displaying a bright picture is realized.Type: GrantFiled: May 28, 2003Date of Patent: October 30, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yukio Tanaka, Jun Koyama, Mitsuaki Osame, Satoshi Murakami, Hideto Ohnuma, Etsuko Fujimoto, Hidehito Kitakado
-
Patent number: 7285828Abstract: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region.Type: GrantFiled: January 12, 2006Date of Patent: October 23, 2007Assignee: Intersail Americas Inc.Inventors: Javier A. Salcedo, Juin J. Liou, Joseph C. Bernier, Donald K. Whitney
-
Patent number: 7285837Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.Type: GrantFiled: January 17, 2005Date of Patent: October 23, 2007Assignee: System General Corp.Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu G. Lin, Ta-yung Yang
-
Patent number: 7271433Abstract: A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pillar. A drain region of the second conductivity type is formed in an upper region of the pillar. A gate dielectric and conductor are arranged along a first side of the pillar. A capacitor dielectric and body capacitor plate are arranged along an opposite, second side of the pillar. A depletion region around the source region defines a floating body region within the pillar which forms both a body of an access transistor structure and a plate of a capacitor structure. The cell also provides gain with respect to charge stored within the floating body.Type: GrantFiled: September 2, 2004Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 7268398Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.Type: GrantFiled: August 14, 2006Date of Patent: September 11, 2007Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
-
Patent number: 7262469Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.Type: GrantFiled: December 15, 2003Date of Patent: August 28, 2007Assignee: Sharp Kabushiki KaishaInventor: Naoki Makita
-
Patent number: 7253453Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.Type: GrantFiled: May 21, 2003Date of Patent: August 7, 2007Assignee: Industrial Technology Research InstituteInventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang
-
Patent number: 7250660Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.Type: GrantFiled: July 14, 2004Date of Patent: July 31, 2007Assignee: Altera CorporationInventors: Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey Tyhach, Guu Lin, Chiakang Sung, Stephanie T. Tran
-
Patent number: 7242059Abstract: A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a source formed in the P-type semiconductor substrate on a main surface of the P-type semiconductor substrate. The CMOS transistor is disposed on the P-type semiconductor substrate and includes a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor is formed in an N-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The N-channel MOS transistor is formed in a P-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The P-type region is electrically isolated from the P-type semiconductor substrate by the N-type region.Type: GrantFiled: February 3, 2004Date of Patent: July 10, 2007Assignee: Ricoh Company, Ltd.Inventors: Takaaki Negoro, Keiji Fujimoto, Takeshi Kimura
-
Patent number: 7242061Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.Type: GrantFiled: January 14, 2003Date of Patent: July 10, 2007Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
-
Patent number: 7235846Abstract: The present invention provides an ESD protection device or structure that exploits the high conductivity of a heavily doped heterojunction base of a standard SiGe bipolar junction transistor (BJT) cell. This improved ESD protection scheme further uses the combination of trench isolation and buried subcollector layer of the SiGe BJT to confine ESD current, minimizing parasitic substrate leakage and achieving large forward voltages while imposing minimal parasitic capacitive loads on a protected active device. Since the ESD protection structure is formed from conventional SiGe BJT transistor cells through modification of the contact metallization, it can be fabricated in an available SiGe BiCMOS fabrication process without additional processing steps, and characterization data already available for the SiGe BJTs can be used to model the performance of the ESD protection devices.Type: GrantFiled: April 27, 2005Date of Patent: June 26, 2007Assignee: WJ Communications, Inc.Inventor: Greg Fung
-
Patent number: 7230303Abstract: The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minority carriers having less mobility. A fabrication process for the semiconductor memory includes a “non-retrograde” implant of impurity ions that is effective to suppress the mobility and lifetime of minority carriers in the devices, and a “retrograde” implant of impurity ions that is effective to substantially increase the doping concentration at the well bottom to slow down or eliminate additional minority carriers.Type: GrantFiled: October 15, 2004Date of Patent: June 12, 2007Assignee: GSI Technology, Inc.Inventor: I Chi Liao
-
Patent number: 7217984Abstract: A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant structure. The divided drain implant structure further comprises at least two drain implant regions separated by a lightly doped drain region and a halo implant region formed underneath. At least one of the drain implant regions is coupled to an input/output pad of a circuit.Type: GrantFiled: June 17, 2005Date of Patent: May 15, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chang Huang, Yu-Hung Chu
-
Patent number: 7217980Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.Type: GrantFiled: September 30, 2004Date of Patent: May 15, 2007Assignee: United Microelectronics Corp.Inventors: Shiao-Shien Chen, Tien-Hao Tang, Mu-Chun Wang
-
Patent number: 7211868Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.Type: GrantFiled: March 16, 2001Date of Patent: May 1, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Hirokazu Fukuda, Hiroki Etou, Kouji Takahashi
-
Patent number: 7208779Abstract: A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.Type: GrantFiled: August 10, 2004Date of Patent: April 24, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masako Ohta, Tsuneaki Fuse
-
Patent number: 7205613Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosedType: GrantFiled: January 7, 2005Date of Patent: April 17, 2007Assignee: Silicon PipeInventors: Joseph C. Fjelstad, Kevin P. Grundy
-
Patent number: 7205612Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.Type: GrantFiled: November 1, 2004Date of Patent: April 17, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jun Cai, Keng Foo Lo
-
Patent number: 7202536Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: GrantFiled: January 28, 2004Date of Patent: April 10, 2007Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
-
Patent number: 7196377Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.Type: GrantFiled: April 22, 2005Date of Patent: March 27, 2007Assignee: NEC Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata, Morihisa Hirata
-
Patent number: 7196379Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.Type: GrantFiled: October 18, 2004Date of Patent: March 27, 2007Assignee: Fujitsu LimitedInventors: Tomonari Morishita, Hideo Nunokawa, Suguru Tachibana, Fukuji Kihara
-
Patent number: 7196378Abstract: A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistor 11 are connected respectively to an output electrode and to ground, is an NMOS protection transistor 10 of which the drain and source are connected respectively to the drain and source of the NMOS output transistor 11 and of which the gate is directly connected to a second-conductivity-type layer, a P-well 22, under the gate electrode of the NMOS output transistor 11. By this means, an electrostatic surge does not concentrate in the NMOS output transistor 11.Type: GrantFiled: March 29, 2004Date of Patent: March 27, 2007Assignee: Oki Electric Indusrty Co., Ltd.Inventor: Kenji Ichikawa
-
Patent number: 7193269Abstract: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation regions, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.Type: GrantFiled: December 9, 2002Date of Patent: March 20, 2007Assignee: NEC CorporationInventors: Akio Toda, Haruihiko Ono
-
Patent number: 7176522Abstract: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.Type: GrantFiled: August 11, 2004Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shui-Ming Cheng, Hung-Wei Chen, Zhong Tang Xuan
-
Patent number: 7176529Abstract: A semiconductor device includes a semiconductor substrate having a resistivity of at least 30 ?·cm, a first MISFET formed on the semiconductor substrate to function as a protective element, and a second MISFET protected by the first MISFET.Type: GrantFiled: May 18, 2004Date of Patent: February 13, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Tatsuya Ohguro
-
Patent number: 7166853Abstract: A system for electrically contacting a semiconductor wafer during implanting of the wafer includes one or more pairs of closely spaced contacts located adjacent the semiconductor wafer and a driving circuit connected to the contacts to provide a discharge from one contact to the semiconductor wafer and from the semiconductor wafer to the other contact of each pair of contacts. The contacts can be spaced apart from the wafer and the tips of the contacts closest to the wafer may have sharp points to aid in the establishment of corona at lower drive voltages. Alternately, the contacts may be rounded and may contact the wafer. The driving circuit may be adapted from a pulsed discharge circuit, such as a Kettering ignition circuit, a capacitance discharge ignition circuit, or a blocking oscillator circuit. Alternately, the driving circuit may be adapted from a continuous discharge circuit, such as a Tesla coil circuit.Type: GrantFiled: September 11, 2002Date of Patent: January 23, 2007Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Kevin G. Rhoads
-
Patent number: 7154721Abstract: An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor. The first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.Type: GrantFiled: December 27, 2005Date of Patent: December 26, 2006Assignee: Hynix Semiconductor Inc.Inventor: Kwang-Myoung Rho
-
Patent number: 7154150Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n?/p?/n?/n+ regions. The emitter is formed of the second N+ region and the second N? well. The parasitic base is formed by the p? substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n? well (emitter) and P? substrate (base) and the junction between P? substrate (base) and the n? well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region.Type: GrantFiled: August 26, 2004Date of Patent: December 26, 2006Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai
-
Patent number: 7154151Abstract: A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.Type: GrantFiled: December 20, 2004Date of Patent: December 26, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Minami
-
Patent number: 7151298Abstract: An electrostatic discharge protection network comprising electrostatic discharge (ESD) clamp devices distributed between turns of a coil shaped inductor. The inductance of the coil shaped inductor and parasitic capacitance of the ESD clamp devices form a low pass filter structure having a very high cut-off frequency. Below the low pass filter cutoff frequency, the capacitive influence of the ESD clamp devices are cancelled by the series inductance of the coil shaped inductor. The turns of the coil shaped inductor may be fabricated on insulation layers proximate to one another so as to achieve close magnetic coupling there between, thereby achieving a larger inductance value for a given sized coil structure. Improved input and output impedance matching is also achieved by adjusting the inductive and capacitive components of the low pass filter structure formed by the coil shaped inductor and capacitance of the ESD clamp devices.Type: GrantFiled: December 20, 1999Date of Patent: December 19, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Dietmar Eggert, Wolfram Kluge
-
Patent number: 7145204Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).Type: GrantFiled: April 15, 2005Date of Patent: December 5, 2006Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli, John E. Kunz, Jr.
-
Patent number: 7145166Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.Type: GrantFiled: August 19, 2004Date of Patent: December 5, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Chin Lee
-
Patent number: 7141854Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.Type: GrantFiled: July 5, 2005Date of Patent: November 28, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yong Meng Lee, Da Jin, David Vigar
-
Patent number: 7135743Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.Type: GrantFiled: December 1, 2005Date of Patent: November 14, 2006Assignees: Chartered Semiconductor Manufacturing Ltd., Agilent Technologies, Inc.Inventors: Indrajit Manna, Keng Foo Lo, Pee Ya Tan, Michael Cheng
-
Patent number: 7129546Abstract: An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is formed adjacent to the first side. The drain region which has a heavily doped region and a lightly doped region formed below the heavily doped region is formed adjacent to the second side. The width along a longitudinal axis of the heavily doped region has variable length and thus the length between one side of the heavily doped region to the second side has variable length.Type: GrantFiled: November 19, 2004Date of Patent: October 31, 2006Assignee: Vanguard International Semiconductor CorporationInventors: Ming-Dou Ker, Kun-Hsien Lin, Geeng-Lih Lin
-
Patent number: 7115952Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: July 1, 2005Date of Patent: October 3, 2006Assignee: Broadcom CorporationInventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
-
Patent number: 7110229Abstract: An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.Type: GrantFiled: May 7, 2004Date of Patent: September 19, 2006Inventors: Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng
-
Patent number: 7102197Abstract: A salicide block area is provided around a gate electrode. Polysilicon coupling portions are formed, which extend at plurality of points from the gate electrode to an area outside of an active region. A contact provided at this inactive region electrically connects the gate electrode to gate electrode metal wiring, which is provided above the gate electrode.Type: GrantFiled: January 30, 2004Date of Patent: September 5, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Kenji Ichikawa
-
Patent number: 7102167Abstract: A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided through the one well into the substrate. Each of the slots are oxidized. Each of the plurality of slots are filled with metal to provide a plurality of power busses. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector. This results in the buried power buss metal always having oxide isolated surroundings. This feature allows all of these power busses to be established wherever necessary without causing any circuit issues since they are always insulated from other areas of the device. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.Type: GrantFiled: April 29, 2002Date of Patent: September 5, 2006Assignee: Micrel, Inc.Inventor: John Durbin Husher
-
Patent number: 7098522Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.Type: GrantFiled: October 4, 2004Date of Patent: August 29, 2006Assignee: Vanguard International Semiconductor CorporationInventors: Geeng-Lih Lin, Yeh-Ning Jou, Ming-Dou Ker
-
Patent number: 7098509Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.Type: GrantFiled: January 2, 2004Date of Patent: August 29, 2006Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peter J. Zdebel, Diann Michelle Dow
-
Patent number: 7095065Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.Type: GrantFiled: August 5, 2003Date of Patent: August 22, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Shibly S. Ahmed, Haihong Wang
-
Patent number: 7091588Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: GrantFiled: December 30, 2004Date of Patent: August 15, 2006Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
-
Patent number: 7078766Abstract: A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the VCC and VSS. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.Type: GrantFiled: May 24, 2001Date of Patent: July 18, 2006Assignee: Taiwan Semiconductor Mfg. Corp.Inventor: Min-hwa Chi