Abstract: A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface and an active device region. First through fourth surface contact areas at the first main surface are arranged directly one after another along a lateral direction. The semiconductor body is electrically contacted at each surface contact area. First and third SCR regions of a first conductivity type directly adjoin the first and third surface contact areas, respectively. Second and fourth SCR regions of a second conductivity type directly adjoin the second and fourth surface contact areas, respectively. The second SCR region at least partially overlaps a first well region of the first conductivity type at the first main surface. The first SCR region at most partially overlaps the first well region at the first main surface, and is electrically connected to the second SCR region. The third SCR region is electrically connected to the fourth SCR region.

Abstract: A semiconductor device includes a protected element and a connection section. The protected element is configured including a diode having an anode region and a cathode region. The diode is arranged on an active layer of a substrate including the active layer formed over a conductive substrate-support with an insulation layer interposed therebetween. The connection section electrically connects the cathode region of the protected element to the substrate-support.

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: A silicon-controlled-rectifier electrostatic protection structure and a fabrication method are provided. The structure includes: a substrate of P-type; a first N-type well, a second N-type well, and a third N-type well in the substrate; a first P-type doped region in the first N-type well; first N-type doped regions at sides of the first N-type well along a first direction; first gate structures on a portion of the first N-type doped regions and on a portion of the first P-type doped region; second gate structure groups at sides of the first N-type well along a second direction; second N-type doped regions in the substrate at sides of each second gate structure along the first direction; second P-type doped regions in the second N-type doped regions between adjacent second gate structure groups; and a third P-type doped region and a cathode N-type doped region in the substrate.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.

Abstract: A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

Abstract: A display includes an antistatic circuit between a common wire and at least one of a signal wire and a scanning wire. The common wire is disposed in a non-display region, and receives a common potential. The signal and scanning wires are disposed in a display region. The antistatic circuit at least includes a first transistor having a floating control electrode, a first main electrode connected to the signal wire or the scanning wire, and a second main electrode connected to the common wire. The first transistor is provided in such a manner that a first capacitance between the control electrode and the signal wire or the scanning wire is larger than a second capacitance between the control electrode and the common wire.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A silicon-controlled-rectifier electrostatic protection structure and a fabrication method are provided. The structure includes: a substrate of P-type; a first N-type well; a second N-type well; a third N-type well; an anode P-type doped region in the first N-type well; second N-type doped regions at sides of the first N-type well; first P-type doped regions at sides of the first N-type well; third N-type doped regions at sides of the first N-type well; gate structures and fourth N-type doped regions at the sides of the first N-type well; and fifth N-type doped regions at the sides of the first N-type well. The fourth N-type doped regions and the third N-type doped regions are disposed at sides of each of the gate structures along a first direction respectively.

Abstract: Provided is a resistor structure of a series resistor of an Electro-Static Discharge (ESD) device. A poly resistor is divided into N small parts, and each small part is connected to an upper-part metal layer through a respectively corresponding Contact and Via. The Contact and Via corresponding to each small part and the connected upper-part metal layer form an independent unit. A metal aluminum material is adopted for the Via and the upper-part metal layer. The metal aluminum material or an aluminum alloy material is adopted for the Contact. A heat capacity characteristic of metal aluminum is utilized, and an existing structure is ingeniously utilized, so that the resistor may be prevented from being damaged by heating caused by the same ESD current, and meanwhile, an overall size of a circuit where the ESD device is located is greatly reduced.

Abstract: In a protective circuit of a conventional electronic device, surge resistance is low and it is difficult to connect an external connection terminal of an integrated circuit directly to an external connection terminal of the electronic device or the like. A protective circuit of an electronic device according to the present embodiment includes an external connection terminal 1 which is connected to an external signal; a wiring layer 2 which connects the external connection terminal 1 and a protective resistor 3; a protective resistor 3 which protects an internal circuit from surges or noises input from the external connection terminal 1; slits which divide the protective resistor 3; current distribution resistors which are constituted by dividing the protective resistor 3 by the slits; and MOS transistors which are connected to the current distribution resistors.

Abstract: A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N? type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and plural polycrystalline plugs. The N? type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the N? type epitaxial layer to form a working-voltage terminal. The first N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is connected with the working-voltage terminal. The deep N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is spaced apart from the first N+ type implant layer at a separation distance. The plural polycrystalline plugs are connected between the working-voltage terminal of the first metal layer and the deep N+ type implant layer.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

Abstract: A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.

Abstract: A chip serving as an individual substrate includes an internal circuit, and an external coupling terminal serving as a first coupling terminal arranged on a first side of the chip. One end side of the external coupling terminal is electrically coupled, via a first electrostatic protection circuit, to a guard line serving as a first common wiring extending along the first side, and another end side is electrically coupled to the internal circuit via a coupling wiring serving as a first coupling wiring. An internal circuit side of the coupling wiring is electrically coupled, via a second electrostatic protection circuit, to a guard line serving as a second common wiring extending along a second side intersecting the first side.

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: A semiconductor device includes first and second exposed electrical contacts and a cavity having a microelectromechanical system (MEMS) structure therein. A conductive path extends from the first exposed electrical contact to the cavity and an over-voltage protection element electrically is coupled between the first and second exposed electrical contacts.

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Abstract: An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.

Abstract: Disclosed is a bidirectional scanning gate drive circuit and a liquid crystal display panel. The technical problem to be solved is that gate drive circuits in the prior art are provided with only one drive mode. The bidirectional scanning gate drive circuit includes an input part, a control part, and an output part. Signals enter the control part from the input part and then enter the output part or signals enter the control part from the output part and then enter the input part, so as to realize driving of a horizontal scanning line in an Nth stage.

Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.

Abstract: A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.

Abstract: A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Abstract: A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Abstract: A bi-directional ESD protection device for an RF circuit that utilizes two pre-driver FETs to reliably maintain the gate voltage of a ggNMOS-type main transistor the lowest applied voltage (e.g., 0V) in order to maximize the main transistor's drain-to-source breakdown voltage, which determines the trigger voltage of the ESD protection device. One pre-driver FET couples the main transistor's gate to ground during positive voltage input signal phases, and the other pre-driver FET couples the main transistor's gate to the input signal path during negative voltage input signal phases. While the amplitude of the input signals remains below the main transistor's trigger voltage, the main transistor remains completely turned off, whereby the input signals are passed to I/O circuitry with minimal interference. Whenever the input signal exceeds the trigger voltage, the main transistor turns on to shunt the over-voltage/current to ground, thereby protecting the I/O circuitry.

Abstract: The present disclosure provides a substrate, including: a first line; a second line; a thin-film transistor (TFT) between the first line and the second line, having a floating gate structure, a source electrode electrically connected to the first line, and a drain electrode electrically connected to the second line; and a first point-discharge structure between the floating gate structure of the TFT and the first line.

Abstract: An enhanced layout for a multiple-finger ESD protection device has several embodiments. In these embodiments, the base contacts of the NPN (or PNP) transistors utilized as voltage clamps in the multiple-finger NPN-based (or PNP-based) multiple-finger ESD protection device are disposed at opposite edges of the multiple-finger ESD protection device and oriented perpendicularly to the orientation of the fingers in the multiple-finger ESD protection device. Similarly, the body contacts of the NMOS (or PMOS) transistors utilized as voltage clamps in the multiple-finger NMOS-based (or PMOS-based) multiple-finger ESD protection device are disposed at opposite edges of the multiple-finger ESD protection device and oriented perpendicularly to the orientation of the fingers in the multiple-finger ESD protection device.

Abstract: The invention provides an ESD (Electrostatic Discharge) protection circuit including a clamp circuit, a switch element, and a detection circuit. The clamp circuit is coupled between an ESD bus and a ground node. The switch element is coupled between a supply node and the ESD bus. The detection circuit is configured to detect whether an ESD event occurs. When no ESD event occurs, the detection circuit closes the switch element, such that the ESD bus is coupled to the supply node. When the ESD event occurs, the detection circuit opens the switch element, such that the ESD bus is decoupled from the supply node.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract: A current level extraction method for preventing cutoff is disclosed. The method may include starting a voltage sweep to an interconnection structure at a certain temperature, measuring an initial resistance of the interconnection structure, calculating a measured resistance of the interconnection structure according to a corresponding input voltage, determining whether or not a resistance ratio of the measured resistance of the interconnection structure to the initial resistance is equal to or less than a preset value, updating a current value corresponding to measured resistance to a potential maximum current level and repeating the step of calculating the measured resistance when the resistance ratio of the interconnection structure is equal to or less than the preset value, and setting the current value corresponding to the measured resistance as a maximum current level when the resistance ratio of the interconnection structure is greater than the preset value.

Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.

Abstract: An object of the present invention is to provide a display device having a function of performing display that is less likely to cause eye strain. In the configuration of the display device of the present invention, one of a source and a drain of a transistor (510) is electrically connected to one electrode of a resistor (580) and one electrode of a first capacitor (550), the other electrode of the resistor (580) is electrically connected to a first wiring (610), the other of the source and the drain of the transistor (510) is electrically connected to one electrode of a liquid crystal element (570) and one electrode of a second capacitor (560), and a gate of the transistor (510) is electrically connected to a second wiring (620).

Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.

Abstract: A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

Abstract: A semiconductor device used in a protection circuit including a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R, the semiconductor device may include: a semiconductor layer in which the thyristor is provided; an insulating film provided on the semiconductor layer; and a pair of electrodes provided on the insulating film and connected to a protection target circuit, wherein at least one of the coil L, the capacitor C and the resistor R is provided in the insulating film, and the at least one of the coil L, the capacitor C and the resistor R is connected to an anode of the thyristor by a first metal wire filling a first hole provided in the insulating film.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile.

Abstract: In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: A semiconductor device that improves the discharge capacity with respect to ESD without increasing the surface area of the semiconductor device includes a first conductive portion including plural portions, each of the plural portions having a first type of conductivity, and each of the plural portions extending in a first direction and being arranged in parallel at a distance from each other in a second direction that intersects the first direction; and a second conductive portion including an island portion provided between the respective plural portions of the first conductive portion and extending in the first direction, the second conductive portion having a second type of conductivity that is different from the first type of conductivity.