Abstract: An integrated circuit includes a first transistor having a first gate and a first source and a second transistor having a second gate and a second source. The integrated circuit includes a first source contact adjacent the second transistor and coupled to the first source and the second source. The integrated circuit includes a first bond wire coupled to the first source contact.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction; a plurality of drain layers which is formed in the semiconductor layer and extends along with the source layers; a plurality of body regions which is provided between the source layers and the drain layers in the semiconductor layer and extends in the first direction; and at least one body connecting part connecting the plurality of body regions, wherein a first width between the source layer and the drain layer at a first position is larger than a second width between the source layer and the drain layer at a second position, the second position is closer to the body connecting part than the first position.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: An ESD protection device for an I/O pad (401); the device comprising a MOS transistor (420) having at least one elongated source region (422) and at least one elongated drain region (421) in a substrate (400) of first conductivity, the length (420a) of the source and drain regions oriented in a direction, the source tied to ground potential (430); a diode having an area including at least one elongated anode region and at least one elongated cathode region in a well of opposite conductivity, the lengths of the anode and cathode regions oriented in the same direction as the transistor regions; the diode area and the well divided normal to the lengths of the anode and cathode regions into two portions (anode portions 411x, 411y, cathode portions 412x, 412y, length portions 410x, 410y, well portions 440x, 440y); and the anode portions connected to the I/O pad, and the cathode portions connected to the transistor drain.

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.

Abstract: An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: The protection element of the present invention is constructed of a MOS capacitor composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate and a word line formed on the insulating film. A well region having a conductivity type opposite to that of the semiconductor substrate is formed in a portion of the semiconductor substrate constituting the MOS capacitor. If charge exceeding the breakdown voltage of the insulating film constituting the MOS capacitor is induced in the word line, the induced charge is released into either the semiconductor substrate or the well region depending on whether the induced charge is positive or negative.

Abstract: A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.

Abstract: An output side of a driver output circuit of an LCD driver includes a first protective element having an n-type semiconductor region and a p-type semiconductor region formed in the n-type semiconductor region, and a second protective element having a p-type semiconductor region and an n-type semiconductor region formed in the p-type semiconductor region. The first and second protective elements are arranged in twos, respectively, adjacent to each other.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A design structure for electrostatic discharge protection comprises a first data representing a first electrostatic discharge (ESD) protection circuit and a second data representing a second ESD protection circuit. A parallel connection of two ESD protection units, each providing a discharge path for electrical charges of opposite types, provides ESD protection circuit for positive and negative voltage swings in the circuit. Each of the multiple emitter-base regions are cascaded such that the base of one emitter-base region is directly wired to the emitter of an adjacent emitter-base region. The first data represents a first ESD protection unit providing protection on one type of voltage swing, and the second data represents a second ESD protection unit providing protection on the other type of voltage swing.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

Abstract: Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract: A field transistor for electrostatic discharge (ESD) protection and method for making such a transistor is described. The field transistor includes a gate conductive layer pattern formed on a field oxide layer. Since the gate conductive layer pattern is formed on the field oxide layer, a thin gate insulating layer having a high possibility of insulation breakdown is not used. To form an inversion layer for providing a current path between source and drain regions, a field oxide layer is interposed to form low concentration source and drain regions overlapped by the gate conductive layer pattern.

Abstract: An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

Abstract: A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region.

Abstract: A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.

Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.

Abstract: An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.

Abstract: A semiconductor device includes a principal IGBT controllable in accordance with a gate voltage applied to a gate electrode thereof, a current detecting IGBT connected to the principal IGBT in parallel and a current detecting part including a detecting resistor capable of detecting a current passing through the current detecting IGBT. The base region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other, and the emitter region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other through the detecting resistor.

Abstract: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

Abstract: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.

Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

Abstract: A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

Abstract: A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive.

Abstract: An organic light emitting display and a method for making the same includes protection circuitry to avoid damage from static electricity. The display and method allow performing a lighting test during display manufacturing. The organic light emitting display includes a substrate, a display region on the transparent substrate with a matrix of pixels, and a signal transfer unit on the transparent substrate for transferring lighting test signals to the pixels. The signal transfer unit includes transistors for transferring the lighting test signals and a resistor coupled to drains and gates of the transistors for protecting the transistors against damage from static electricity.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.

Abstract: A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transistor, and a resistor are each disposed on the semiconductor thin film. A second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element is disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film. The second N-channel MOS transistor has a gate electrode, a source region and a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region.

Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.