For Operation As Bipolar Or Punchthrough Element Patents (Class 257/361)
  • Patent number: 11177252
    Abstract: The semiconductor device and the method of fabricating the same includes, on a surface of a semiconductor substrate 1 of a first conductivity type which is P-type or N-type, a diode element using a PN junction including a high-concentration first conductivity type impurity region 6 of the first conductivity type, a high-concentration second conductivity type impurity region 5 of a second conductivity type that is a conductivity type opposite to the first conductivity type, and an element isolation region 2 sandwiched between the high-concentration first conductivity type impurity region and the high-concentration second conductivity type impurity region, and a floating layer 3 of the second conductivity type separated from the high-concentration second conductivity type impurity region below the high-concentration second conductivity type impurity region on the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 16, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyuki Tanaka, Masahiko Higashi
  • Patent number: 10504885
    Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 10, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Sunglyong Kim, David LaFonteese, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 10163891
    Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 10050614
    Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 14, 2018
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Xuefeng Chen
  • Patent number: 9997507
    Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 12, 2018
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou, Peter Almern Losee
  • Patent number: 9948091
    Abstract: Silicon-controlled rectifier (SCR) based circuit for ECG protection under defibrillator pulse is disclosed. The SCR-based clamp is a symmetric structure for dual-direction voltage tolerance protection based on two anti-series P-well/N-well lateral blocking junctions isolated from P-substrate by the N-buried layer. The injector regions (n+/p+) are substantially lengthened in order to accommodate a larger number of contact rows than typically used for ESD pulses specification. A stack of metal layers may also be used to provide high current and heat-sink capability with each electrode metal layer fully filled with VIAs.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 17, 2018
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Douglas Stuart Smith, Vladislav Vashchenko, Augusto Tazzoli, Sudhir Mulpuru, Lawrence Richard Skrenes
  • Patent number: 9929207
    Abstract: A light-emitting device is provided. The light-emitting device comprises: a semiconductor structure comprising a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; and an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; wherein the second part functions as a low-resistance resistor and loses its make diode behavior, the active layer in the first part is capable of generating light, and the active layer in the second part is incapable of generating light.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: March 27, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Rong-Ren Lee, Cheng-Hong Chen, Chih-Peng Ni, Chun-Yu Lin
  • Patent number: 9813052
    Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 7, 2017
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Xuefeng Chen
  • Patent number: 9806157
    Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: October 31, 2017
    Assignee: General Electric Company
    Inventors: Alexander Viktorovich Bolotnikov, Avinash Srikrishnan Kashyap
  • Patent number: 9716016
    Abstract: One or more techniques or systems for forming an electrostatic discharge (ESD) clamp are provided herein. In some embodiments, the ESD clamp includes a first pad and a second pad. For example, the first pad is a positive supply voltage (Vdd) pad and the second pad is a negative supply voltage (Vss) pad. In some embodiments, active regions and oxide regions are associated with substantially rounded shapes or obtuse angles. Additionally, metal regions are configured to be in contact with at least some of at least one of the active regions or the oxide regions and the first pad. In some embodiments, the metal regions are substantially wedge shaped. In this manner, an ESD clamp with enhanced performance is provided, at least because the respective active regions are substantially rounded or associated with obtuse angles, for example.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chia-Wei Hsu
  • Patent number: 9627372
    Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: April 18, 2017
    Assignee: NXP B.V.
    Inventor: Da-Wei Lai
  • Patent number: 9584112
    Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: February 28, 2017
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Xuefeng Chen
  • Patent number: 9543430
    Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Patent number: 9356012
    Abstract: An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 9231402
    Abstract: A circuit device includes a diode bridge having a first power input and a second power input and having a first output terminal and a second output terminal. The diode bridge includes a plurality of diodes and a respective plurality of diode bypass elements associated with the plurality of diodes. The circuit device further includes a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at the first and second output terminals.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 5, 2016
    Assignee: Silicon Laboratories Inc.
    Inventor: D. Matthew Landry
  • Patent number: 9184265
    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yao Lai, Yen-Ming Chen, Shyh-Wei Wang
  • Patent number: 9018071
    Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: April 28, 2015
    Assignee: Freescale Semiconductor Inc.
    Inventors: Rouying Zhan, Amaury Gendron, Chai Ean Gill
  • Patent number: 9006833
    Abstract: A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman
  • Patent number: 8987858
    Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 24, 2015
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
  • Patent number: 8981425
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: March 17, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 8981484
    Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Patent number: 8963277
    Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8946825
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 8916935
    Abstract: A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Fu Huang
  • Patent number: 8890250
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
  • Patent number: 8842400
    Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Shih-Hung Chen, Kun-Hsien Lin
  • Patent number: 8836034
    Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Hirose, Hideaki Shishido
  • Patent number: 8829571
    Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 9, 2014
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Arnost Kopta, Jan Vobecky, Wolfgang Janisch
  • Patent number: 8796729
    Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Analog Devices, Inc.
    Inventors: David J Clarke, Javier Alejandro Salcedo, Brian B Moane, Juan Luo, Seamus Murnane, Kieran K Heffernan, John Twomey, Stephen Denis Heffernan, Gavin Patrick Cosgrave
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8717724
    Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: May 6, 2014
    Assignee: Soongsil University research Consortium techno-Park
    Inventors: Joon Young Park, Jong Hoon Park, Chang Kun Park
  • Patent number: 8710590
    Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: April 29, 2014
    Assignee: Infineon Technologies AG
    Inventors: Philipp Riess, Henning Feick, Martin Wendel
  • Patent number: 8710547
    Abstract: The inventive concept provides avalanche photo diodes and methods of manufacturing the same. The avalanche photo diode may include a substrate, a light absorption layer formed on the substrate, a clad layer formed on the light absorption layer, an active region formed in the clad layer, a guard ring region formed around the active region, and an insulating region formed between the guard ring region and the active region.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 29, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Sik Sim, Kisoo Kim, Bongki Mheen, MyoungSook Oh, Yong-Hwan Kwon, Eun Soo Nam
  • Patent number: 8691684
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 8, 2014
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Guo Hua Zhong, Mei Yang
  • Patent number: 8680621
    Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: March 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrice Besse, Jean Philippe Laine
  • Patent number: 8653627
    Abstract: A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 18, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Patent number: 8647955
    Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rouying Zhan, Amaury Gendron, Chai Ean Gill
  • Patent number: 8648419
    Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amaury Gendron, Chai Ean Gill, Changsoo Hong
  • Patent number: 8592910
    Abstract: A semiconductor body includes a protective structure. The protective structure (10) includes a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure includes an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 26, 2013
    Assignee: AMS AG
    Inventor: Hubert Enichlmair
  • Patent number: 8558276
    Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: October 15, 2013
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventor: Madhur Bobde
  • Patent number: 8530970
    Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Felix Patrick Anderson, Thomas Leddy McDevitt, Anthony Kendall Stamper
  • Patent number: 8471292
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 25, 2013
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Cornelius Christian Russ, Kai Esmark
  • Patent number: 8460994
    Abstract: A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 11, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Patent number: 8390071
    Abstract: A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rouying Zhan, Amaury Gendron, Chai Ean Gill
  • Patent number: 8324658
    Abstract: An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Chewn-Pu Jou, Fu-Lung Hsueh, Ming-Hsiang Song
  • Patent number: 8324688
    Abstract: The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: December 4, 2012
    Assignee: Bauabtech
    Inventor: Kilho Kim
  • Patent number: 8253203
    Abstract: An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond (input or output) pad and a substantially fixed voltage level (e.g., a ground (or zero potential) or Vcc, depending on the transistor configuration) in a semiconductor electronic device so as to protect transistor gates or other circuit portions from damage from electrostatic voltages. The parasitic BJTs and the field transistor may be configured to remain cut off so long as an input voltage at the pad is between a negative V1 voltage (?V1) (V1>0) and a +V2 voltage (V2>Vcc), thereby allowing a greater input voltage swing without signal clamping.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joohyun Jin
  • Patent number: 8253165
    Abstract: A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 28, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Yu Wang, Chia-Ling Lu, Yan-Yu Chen, Yu-Lien Liu, Tao-Cheng Lu
  • Patent number: 8188545
    Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 29, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Saiki, Satoru Ito, Masahiko Moriguchi
  • Patent number: 8138550
    Abstract: A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: March 20, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hajime Kurata