Abstract: An electrostatic protection element including: a first impurity layer of second conductivity type formed on a semiconductor substrate of first conductivity type; a second impurity layer of the first conductivity type formed within the first impurity layer; a first contact layer of the first conductivity type formed in a region within the first impurity layer other than at the second impurity layer; a second and a third contact layer both of the second conductivity type and formed within the second impurity layer; and multilayer wiring connected through a stack structure to the first, the second, and the third contact layer, wherein the stack structure includes at least a first layer wiring connected to each of the first, the second, and the third contact layer, and a second layer wiring connected to the first layer wiring directly above each of the first, the second, and the third contact layer.

Abstract: A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

Abstract: The present disclosure provides a diode chip capable of attaining excellent electrical characteristics. The present disclosure provides a diode chip (1), including: a semiconductor chip (10) having a first main surface (11); a first pin junction portion (31) formed on a surface of the first main surface (11) with a first polarity direction; a first diode pair (37) (rectifier pair) including a first pn junction portion (35) separated from the first pin junction portion (31) and formed in the semiconductor chip (10) with the first polarity direction and a first reversed pin junction portion (38) connected to the first pn junction portion (35) in reversed direction and formed on the first main surface (11) with a second polarity direction; and a first junction separation trench (46) formed on the first main surface (11) in a manner of separating the first pin junction portion (31) and the first diode pair (37).

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge devices and methods of manufacture. The structure includes: a plurality of regions of a first dopant type; insulator material separating each region of the plurality of regions of the first dopant type; and a substrate contacting the plurality of regions of the first dopant type, the substrate comprising a base region of a second dopant type different than the first dopant type and an outer segment surrounding the plurality of regions of the first dopant type, the outer segment comprises an electrical resistivity higher than the second dopant type.

Abstract: A semiconductor device includes an electrostatic protection circuit 1 and a MOSFET 2 including a gate terminal. The electrostatic protection circuit 1 includes a positive-side power supply terminal 3, a negative-side power supply terminal 5, a first protection diode 4, a second protection diode 6, a resistance element 7, and a bipolar transistor 8. The second protection diode 6 includes an anode terminal electrically connected to the negative-side power supply terminal 5 via the resistance element 7, and a cathode terminal electrically connected to the gate terminal. The bipolar transistor 8 includes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistor 8 is electrically connected to the anode terminal of the second protection diode 6, the gate terminal, and the positive-side power supply terminal 3. The electrostatic protection circuit 1 is formed on a semiconductor substrate made of silicon carbide.

Abstract: The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.

Abstract: A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer.

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: An electrostatic discharge (ESD) protection circuit includes a plurality of transistors each including a gate terminal, a drain terminal, and a source terminal, a first connection line connected to the drain terminals of the plurality of transistors, a second connection line connected to the source terminals of the plurality of transistors, a third connection line connected to the gate terminals of the plurality of transistors, an external resistor connected to the third connection line, and a ground terminal connected to the external resistor. The external resistor includes a first resistor and a second resistor connected to each other in parallel.

Abstract: A MOS cell based on a simple and self-aligned process is provides a planar cell forming a horizontal MOS channel, and a plurality of trench regions, which are arranged at an angle with respect to the longitudinal direction of the planar cells. The new cell concept can adopt both planar MOS channels and Trench MOS channels in a single MOS cell structure, or planar MOS channels alone, while utilising the trenches to improve the current spreading of the planar MOS channels. Floating P-doped regions at the bottom of the trench regions protect the device against high peak electric fields. The orthogonal trench recesses are discontinued in their longitudinal direction to allow the planar channels to conduct electrons. The design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials.

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

Abstract: The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.

Abstract: The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: a P-type substrate; an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and the N-type well 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode is in mirror symmetry with a second electrode with respect to the P-type heavily doped region 24, and shallow trench isolations are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and the N-type heavily doped region 26.

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

Abstract: The semiconductor device and the method of fabricating the same includes, on a surface of a semiconductor substrate 1 of a first conductivity type which is P-type or N-type, a diode element using a PN junction including a high-concentration first conductivity type impurity region 6 of the first conductivity type, a high-concentration second conductivity type impurity region 5 of a second conductivity type that is a conductivity type opposite to the first conductivity type, and an element isolation region 2 sandwiched between the high-concentration first conductivity type impurity region and the high-concentration second conductivity type impurity region, and a floating layer 3 of the second conductivity type separated from the high-concentration second conductivity type impurity region below the high-concentration second conductivity type impurity region on the semiconductor substrate.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: Silicon-controlled rectifier (SCR) based circuit for ECG protection under defibrillator pulse is disclosed. The SCR-based clamp is a symmetric structure for dual-direction voltage tolerance protection based on two anti-series P-well/N-well lateral blocking junctions isolated from P-substrate by the N-buried layer. The injector regions (n+/p+) are substantially lengthened in order to accommodate a larger number of contact rows than typically used for ESD pulses specification. A stack of metal layers may also be used to provide high current and heat-sink capability with each electrode metal layer fully filled with VIAs.

Abstract: A light-emitting device is provided. The light-emitting device comprises: a semiconductor structure comprising a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; and an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; wherein the second part functions as a low-resistance resistor and loses its make diode behavior, the active layer in the first part is capable of generating light, and the active layer in the second part is incapable of generating light.

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.

Abstract: One or more techniques or systems for forming an electrostatic discharge (ESD) clamp are provided herein. In some embodiments, the ESD clamp includes a first pad and a second pad. For example, the first pad is a positive supply voltage (Vdd) pad and the second pad is a negative supply voltage (Vss) pad. In some embodiments, active regions and oxide regions are associated with substantially rounded shapes or obtuse angles. Additionally, metal regions are configured to be in contact with at least some of at least one of the active regions or the oxide regions and the first pad. In some embodiments, the metal regions are substantially wedge shaped. In this manner, an ESD clamp with enhanced performance is provided, at least because the respective active regions are substantially rounded or associated with obtuse angles, for example.

Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.

Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor. The pull-down path includes a diode-connected MOS transistor coupled in parallel with a second MOS transistor that couples the gate terminal of the switching MOS transistor to ground via third and fourth MOS transistors when the switching MOS transistor is in an OFF state. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage, VDD, to activate the pull-down path. A capacitor may be coupled between gate and source terminals of the switching MOS transistor to switch the switching MOS transistor to an ON state.

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract: An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.

Abstract: A circuit device includes a diode bridge having a first power input and a second power input and having a first output terminal and a second output terminal. The diode bridge includes a plurality of diodes and a respective plurality of diode bypass elements associated with the plurality of diodes. The circuit device further includes a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at the first and second output terminals.

Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.

Abstract: A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

Abstract: A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.