Abstract: The present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, and a first N-type doped region, are formed on the P-type substrate, wherein the first P-type doped region and the first N-type doped region are coupled to the specific voltage point, respectively. A second P-type doped region and a second N-type doped region are formed on the first N-type well and are coupled to the pad, respectively. Moreover, a third N-type doped region and a fourth N-type doped region are formed on the P-type substrate. The third N-type doped region is coupled to the pad, and a second N-type well is formed between the third N-type doped region and the fourth N-type doped region.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p−, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (=Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD. A punch-through diode according to the invention has an inverted structure, which means that the regions (1, 2, 3, 4) are positioned in reverse order on the substrate (11) and thus, the first region (1) adjoins the surface, and the fourth region (4) adjoins the substrate (11). Such a diode has a very steep I-V characteristic, is very suitable as a TVSD and functions very well at an operating voltage below 5 volts.

Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.

Abstract: An ESD protection circuit having silicon-controlled rectifier structure, includes a PNP transistor and an NPN transistor. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.

Abstract: An integrated circuit device receiving signals from a signal pad that includes at least one silicon bipolar junction transistor responsive to the signals from the signal pad for providing electrostatic discharge protection, and a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one silicon bipolar junction transistor, wherein the at least one silicon bipolar junction transistor includes an emitter, collector and base formed in a single silicon layer and isolated from a substrate of the integrated circuit device, and wherein the base is coupled to the detection circuit to receive the bias voltage.

Abstract: The present invention is related to a semiconductor device for electrostatic discharge or overvoltage protection applications, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages and said means including a series configuration of at least two trigger components. Said means can further be extended with a third trigger component and possibly further trigger components in said series configuration, the addition of said third and further trigger components extending sequentially the range of the intermediate trigger voltages. Said trigger components can comprise components, preferably diodes, with a specific breakdown voltage, the sum of the breakdown voltages of said diodes defining the specific intermediate trigger voltage of said device.

Abstract: In this invention, a novel substrate-triggered technique is proposed to effectively improve the electrostatic discharge (ESD) robustness of integrated circuit (IC) products. The ESD protection circuit derived from the substrate-triggered technique is comprised of a metal-oxide-semiconductor (MOS) transistor and an ESD detection circuit. The MOS transistor is composed of a bulk region, a gate, a source region coupled to a power rail, and a drain region couple to a pad. The source region, the bulk region and the drain region further construct a parasitic bipolar junction transistor (BJT) The ESD detection circuit is located between, and connected to, the power rail and the pad. During normal operation, the ESD detection circuit maintains the coupling of the bulk region to the first power rail. During an ESD event, the ESD detection circuit biases the bulk region to trigger the BJT thereby releasing ESD stress.

Abstract: A semiconductor device protection circuit is composed of a first semiconductor portion of a first conductive type, a second semiconductor portion of a second conductive type connected to the first semiconductor portion, a third semiconductor portion of the first conductive type connect to the second semiconductor portion, and fourth and fifth semiconductor portions of the second conductive type, both connected to the second semiconductor portion. The first conductive portion is connected to a semiconductor circuit which is to be protected from electrostatic breakdown. The third, fourth, and fifth semiconductor portions are short-circuited. The fourth and fifth semiconductor portions are located at opposite sides of the third semiconductor portion.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: A power component is proposed which reliably switches inductive loads and has a current detection element to detect the current through the inductive load. The component includes a protective element which is connected to the source terminals of the sense element and of the actuator. The protective element protects against parasitic effects between the sense element and the actuator.

Abstract: A static protection device protects an internal circuit of a semiconductor device from surge voltages. An emitter terminal of the PNP transistor is connected to the input/output terminal, a collector terminal of the PNP transistor is connected to the ground terminal, and the base terminal is left open, to realize the static protection device. In this manner the reverse-biased protection can be maintained with respect to the internal circuit.

Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.

Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node.

Abstract: A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.

Abstract: An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.

Abstract: In an ESD protection device and method, greater stability is achieved in a MOS device by replacing the thin gate oxide with a shallow trench isolation region, and breakdown voltages are reduced by providing for dynamic substrate control. In the case of NMOS, the dynamic substrate control also has the effect of reducing triggering voltage.

Abstract: There is provided a method of fabricating a silicon-on-insulator substrate, including the steps of (a) forming a silicon substrate at a surface thereof with an oxygen-containing region containing oxygen at such a concentration that oxygen is not precipitated in the oxygen-containing region in later mentioned heat treatment, (b) forming a silicon oxide film at a surface of the silicon substrate, (c) implanting hydrogen ions into the silicon substrate through the silicon oxide film, (d) overlapping the silicon substrate and a support substrate each other so that the silicon oxide film makes contact with the support substrate, and (e) applying heat treatment to the thus overlapped silicon substrate and support substrate to thereby separate the silicon substrate into two pieces at a region into which the hydrogen ions have been implanted, one of the two pieces remaining on the silicon oxide film as a silicon-on-insulator active layer.

Abstract: A bi-directional transient voltage suppression device with symmetric current-voltage characteristics is provided. The device comprises: (a) a lower semiconductor layer of first conductivity type; (b) an upper semiconductor layer of first conductivity type; and (b) a middle semiconductor layer adjacent to and disposed between the lower and upper layers, the middle layer having a second conductivity type opposite the first conductivity type, such that upper and lower p-n junctions are formed. In this device, the middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer and within at least a portion of the lower and upper layers, the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side of the centerplane.

Abstract: A electrostatic discharge (ESD) device with salicide layers isolated by a shallow trench isolation in order to save one salicide block photomask. A shallow trench isolation is formed in drain region to isolate a portion of the drain region, so that the drain region is partitioned into two parts. A salicide layer is formed on the drain region. Since the salicide layer is not formed on the shallow trench isolation, without using an additional photomask, the salicide layer on the drain region is partitioned into two parts. The effect of the local thermal energy occurring to drain junction upon the contact metal of the drain region is eliminated.

Abstract: An ESD protection circuit based on a modification of conventional silicon controlled rectifier (SCR) for preventing integrated circuits from ESD damage. A first N-well, which has a second N-type doped region and third P-type doped region, is formed in a P-type substrate. A fourth N-type doped region and fifth doped region are formed adjacent to the first N-well in the substrate. A first conducting structure is formed on the second N-type doped region and connected to an anode. A second conducting structure is formed on the fourth N-type doped region and fifth P-tape doped region and connected to a reference potential.

Abstract: A novel low-voltage-triggered semiconductor controlled rectified (LVTSCR) as an ESD protection device is provided in this invention. The ESD protection device of the present invention has a lateral SCR (LSCR) structure with two electrodes and a MOS for triggering the LSCR. A dummy gate and a doped region are used to isolate the MOS from one of these two electrodes. The dummy gate is designed to block the formation of field-oxide layer formed in the device structure of the lateral SCR. Therefore, the proposed SCR device has a shorter current path in CMOS process, especially in the CMOS process with shallow trench isolation (STI) field-oxide layer. During an ESD, the current path in the ESD protection device is much shorter, and the turn-on speed and the ESD tolerance level are thereby enhanced.

Abstract: The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2).

Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate, a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor, an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region. the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.

Abstract: A lateral NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a stopping region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate. The transistor further has in its p-well a region of higher resistivity than the remainder of the well. This region extends laterally from the vicinity of one of the recessed region to the vicinity of the other, and vertically from a depth just below the depletion regions of source and drain to the top of the channel stop region. According to the invention, this region of higher p-type resistivity is created by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants adjusting the threshold voltage and creating the p-well and channel stop.

Abstract: A lateral bipolar type input/output protection device of the present invention includes a N type well formed below an emitter impurity diffusion layer of N type over a P type substrate. With such construction of the lateral bipolar type input/output protection device, a parasitic bipolar operation occurs easily and sufficient electrostatic durability without degradation of protection performance of the protection device even when a semiconductor integrated circuit is miniaturized by employing the STI isolation structure.

Abstract: An electrical resistor integrated in an integrated semiconductor circuit to have a useful resistor with two spaced-apart useful resistor terminal contact regions and a useful resistor region of semiconductor material located therebetween; and an auxiliary resistor having two spaced-apart auxiliary resistor terminal contact regions and an auxiliary resistor region located therebetween.

Abstract: An electrostatic discharge (ESD) protection device for protecting semiconductor devices against high-voltage transients due to electrostatic discharges. It includes: (1) an N-type well formed in a P-type semiconductor layer (or P-substrate); (2) a plurality of first P+ regions formed in the P-type semiconductor layer, wherein each of the first P+ regions is connected to an input,pad and is formed inside the N-type well; (3) a plurality of second P+ regions formed in the P-type semiconductor layer, wherein each of the second P+ regions is connected to the ground, at least one of the second P+ regions is outside the N-type well, and at least one of the second P+ regions is either in the N-type well or adjacent to it; and (4) an N+ region formed outside of the N-type well.

Abstract: A MOSFET transistor (2 FIG. 4) contains functional elements that together define an electrical capacitance (20, 27, 10-13) capable of accumulating a static electrical charge transferred from an external source, when the transistor is out of or removed from a circuit. An additional semiconductor device (21, 30, 11, 13) is integrated within said transistor and bypasses electrical charge from the capacitance to prevent such static charge from attaining a level at which said voltage spanning the dielectric element of the capacitance is sufficient to destroy the dielectric element. The foregoing protects the MOSFET and associated circuitry against static electricity without adversely affecting normal operation. In one embodiment, the additional semiconductor device is a lateral bipolar transistor.

Abstract: In a protective circuit, on a semiconductor substrate of a first conduction type an island-shaped first well of a second conduction type for formation of a protective element for bypassing the above-noted static electricity and a second well of the second conduction type biased to a prescribed potential and intended for formation of a circuit element of the internal circuit are formed so as to be mutually separated, the first well and the second well being connected via a resistance. By this configuration, when static electricity is applied the potential of the first well changes in response thereto, and a current flowing from the first well into the second well is appropriately suppressed, thereby preventing destruction of the internal circuit by the static electricity.

Abstract: A MOSFET transistor (2 FIG. 4) contains functional elements that together define an electrical capacitance (20, 27, 10-13) capable of accumulating a static electrical charge transferred from an external source, when the transistor is out of or removed from a circuit. An additional semiconductor device (21, 30, 11, 13) is integrated within said transistor and bypasses electrical charge from the capacitance to prevent such static charge from attaining a level at which said voltage spanning the dielectric element of the capacitance is sufficient to destroy the dielectric element. The foregoing protects the MOSFET and associated circuitry against static electricity without adversely affecting normal operation. In one embodiment, the additional semiconductor device is a lateral bipolar transistor.

Abstract: A semiconductor device has a first semiconductor chip having a device formed thereon and a second semiconductor chip having a protection circuit for protecting the device formed thereon. The second semiconductor chip is superposed on and bonded to the surface of the first semiconductor chip.

Abstract: A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network.

Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive material overlies the insulating layer and makes electrical contact with the semiconductor layer through the contact hole, thereby forming a base contact. The semiconductor layer has a first conductivity type in a central region which substantially underlies the conductive material, and has a second conductivity type in regions adjacent the central region. The first region forms a base region and the adjacent regions form a collector region and an emitter region, respectively. A method of forming a lateral bipolar transistor device is also disclosed. The method includes forming a semiconductor layer over an insulating material and forming an insulating layer over the semiconductor material.

Abstract: An electrostatic discharge protection device for integrated circuit is formed in a substrate and contains pad contact, rail contact and a deep oxide in a trench in the substrate which isolates pad and rail contacts. The substrate is doped with a first dopant type with a first concentration. A second dopant type in a first inner and a first outer region forms the pad contact; both regions are formed on the substrate. The first inner region is doped higher than the first outer region. Similarly a second dopant type in a second inner and a second outer region forms the rail contact; both regions are formed on the substrate. The second inner region is doped higher than the second outer region. Buried layers are formed of the first dopant type in a second concentration under the pad and rail contacts and under the deep oxide.

Abstract: A tunable high voltage trigger silicon controlled rectifier (SCR) with a high holding voltage is disclosed. The source of a drain extended MOS serves as the remote cathode for the SCR, while the drain of the drain extended MOS serves to generate avalanche currents to trigger the SCR.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: The invention provides a semiconductor device that has sufficient device protection capability and besides allows integration of transistors with high density. The semiconductor device includes an NMOS transistor formed in a p-well on a p-type substrate, an n-well formed adjacent the p-well, and first and second protection elements connected to a gate electrode of the NMOS transistor. The first protection element is a pn diode formed from the p-well and an n+ diffusion region provided in the p-well and lets negative charges escape to the p-type substrate. The second protection element is a pn diode formed from the n-well and a p+ diffusion region provided in the n-well, and lets positive charges escape to the p-type substrate as pn junction leakage current between the n-well and the p-type substrate.

Abstract: A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. Ann-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.

Abstract: The invention relates to a bipolar ESD protection comprising a protection transistor with a short-circuited base emitter (18, 19). Due to the snap-back effect, the transistor can switch from the normal high-ohmic condition to a low-ohmic condition in the case of ESD. To improve the protection performance, the protection structure is provided with a trigger element comprising a second transistor (26, 27, 28) with a lower breakdown voltage. The base (26) and the emitter (28) of the second transistor are connected to the base of the protection transistor. To increase the current carrying capability of the protection device, the trigger transistor is designed so as to be a vertical transistor.

Abstract: A new High Dynamic Range charge detection concept useful for CCD and Active Pixel CMOS image sensors uses at least one transistor operating in a punch through mode for the charge detection node reset. The punch through operation significantly reduces the reset feed through which leads to a higher voltage swing available on the node for the signal. This in turn allows building smaller and thus more sensitive charge detection nodes. The undesirable artifacts, associated with the incomplete reset that are induced by the punch through operation, are completely removed by incorporating the CDS signal processing method into the signal processing chain. The incomplete reset artifact removal by the CDS technique is extended to all other resetting concepts that are modeled by a large reset time constant. The punch through concept is suitable for resetting Floating Diffusion charge detection nodes as well as Floating Gate charge detection nodes.

Abstract: An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) which uses low voltage transistors (N1, N2) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a Vox-max suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (250) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (202) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage.

Abstract: A MOS transistor structure is provided for ESD protection in an integrated circuit device. A trench controls salicide deposition to prevent hot spot formation and allows control of the turn-on voltage. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusions on either side of the gate. A drain trench is located to separate the salicide between a drain contact and the gate edge, and by controlling the size and location of the drain trench, the turn-on voltages can be controlled; i.e., the turn-on voltage due to drain diffusion region to substrate avalanche breakdown and the turn-on voltage due to source well to drain well punch-through. Thus, very low turn-on voltages may be achieved for ESD protection.