Abstract: A plurality of Zener diodes are connected between two electrodes of a transistor as the protector of the transistor to obtain a predetermined breakdown voltage. Each Zener diode has a breakdown of 5 V whose temperature coefficient is substantially zero.

Abstract: An electrostatic discharge protection device for protecting the input of a circuit comprises a p-channel MOSFET (P-FET). The n-well with P+ implants of the P-FET provides a functional lateral PNP bipolar transistor that is coupled between the input of the circuit and a supply node of the circuit. Biasing circuitry controls biasing of the gate and n-well body of the P-FET in accordance with the voltage at the input of the circuit.

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract: An input protection circuit for a MOS device uses back-to-back zener diodes 30 and 40 with the anodes 130 and 150 connected and floating. This circuitry protects against positive and negative ESD events and does not interfere with the normal operation of the MOS device. The inventive circuit allows an improved gate operating range of the forward bias voltage of a first diode 30 plus the breakdown voltage of a second diode 40 below the supply voltage to the breakdown voltage of the first diode 30 plus the forward bias voltage of the second diode 40 above the supply voltage.

Abstract: A semiconductor device is disclosed which has an input terminal, an input protective device, a first stage circuit connected between the input terminal and an internal circuit, and a ground line system including a plurality of ground lines divided for noise suppression. Ground nodes of the protective circuit and the first stage circuit are connected with each other and to a common first ground line, while the ground nodes of the internal circuit are connected to second and third ground lines. The parasitic resistance formed between the ground nodes for the protective device and for the first stage circuit is reduced, thereby providing a surge voltage not higher than a clamp voltage of the protective device to protect the first stage circuit against electrostatic discharge-induced failure.

Abstract: An electrical circuit including an NMOS or lateral NPN bipolar transistor includes a zener diode connected thereto to provide ESD protection for the transistor. The NMOS transistor includes an N-type source, an N-type drain, a P-type channel region and a gate over and insulated from the channel region. The zener diode is electrically connected between the gate and the drain of the NMOS transistor with the anode of the zener diode being connected to the gate and the cathode of the zener diode being connected to the drain. For some purposes the anode of the zener diode is positioned close to the gate to provide the desired ESD protection. The lateral NPN bipolar transistor includes an N-type emitter and collector and a P-type base. The zener diode is connected between the collector and the base with the anode of the zener diode being connected to the base and the cathode of the zener diode being connected to the emitter.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A protection circuit structure for an internal semiconductor integrated circuit. The protection circuit structure includes a first protection circuit having at least a first input pin and a first discharge pin, a second protection circuit having at least a second input pin and a second discharge pin and a switching device connecting between the first and second protection circuits. The switching device is biased by a potential difference between the first and second discharge pins. The switching device permits operating one of the first and second protection circuits to accomplish a discharge in replacement of an inoperative first or second discharge pin. The switching device takes the ON state when biased by a predetermined voltage or higher which interrupts the internal semiconductor integrated circuit. The switching device connects between wiring lines which respectively connect to the first and second discharge pins.

Abstract: A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the f

Abstract: A power diode having substantially no reverse-recovery time and relatively high conductance. The power diode is a majority carrier semiconductor having a structure that is similar to that of a metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate, and a body. In one embodiment, to increase conductance of the power diode, a linked-cell configuration that reverses the geometry of a conventional cell-type MOSFET is employed, thereby increasing the width of a conductance channel over that of a conventional MOSFET, and compensating for a relatively low level of inversion in the channel region. Negative and positive feedback circuits are used to further improve the conductance of the power diode by dynamically setting a bias voltage applied between the gate and the source to a level just below a threshold voltage.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: A two-way conductive directional circuit formed in a polycrystalline silicon layer separated by an insulation film from a semiconductive element is one-way biased for sensing a temperature of the semiconductive element. The directional circuit may be provided with a bias in either conductive direction thereof for sensing a temperature of the semiconductive element, before being provided with a bias in the other conductive direction thereof for sensing the temperature of the semiconductive element.

Abstract: A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.

Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: An input protection device comprises a current limiting resistor externally connected to an integrated circuit which includes two Zener diodes, one functioning as a power supply Zener diode and the other functioning as a ground Zener diode. Owing to the resistance of the current limiting resistor and junction capacitances of the Zener diodes, electromagnetic interference noise is effectively damped or attenuated.

Abstract: A semiconductor device has protective devices formed in a P-type semiconductive region maintained at a ground potential and disposed adjacent to bonding pads connected to internal circuitry through respective signal lines. A plurality of first N+ diffusion regions connected to respective signal lines and a second diffusion region connected to a ground line are disposed in the P-type semiconductive region. A separating region having a thick insulating layer is disposed between the first diffusion regions and the second diffusion region. The protective devices formed as NPN transistors have a common emitter at the second N+ diffusion region, which has enough area for storing and discharging electric charges to the ground, while the occupied area of the protective devices is maintained small. The protective devices can be formed as so-called field MOS transistors having a common source.

Abstract: A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.

Abstract: A semiconductor device having an electrostatic discharge protection device, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including, a semiconductor substrate, an epitaxial layer laminated on the semiconductor substrate, a buried collector of a first conductive type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer, a base of a second conductive type which is a lightly doped well and formed on the epitaxial layer, and an emitter of the first conductive type and formed on the surface layer of the base of the second conductive type; and in which the depth of the diffusion of the base being in the range from 0.8 to 2.3 microns, and the base and the emitter being shorted with each other.

Abstract: The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown voltage than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer.Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well for to form drains of another non-LDD NMOS, which are connected to the positive power supply. These non-LDD NMOS act as npn transistor and are turned on when high voltage ESD pulses appears at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals.

Abstract: A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor.

Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.

Abstract: A buried contact module is provided that includes a dopant-diffusion buffer layer. The dopant-diffusion buffer layer is formed with a thin dielectric region fabricated between the polysilicon contact region and the well region. The dielectric region formed of, for example, silicon dioxide, limits the amount of phosphorous diffusion into the well region. Thus, a buried contact junction can be formed in an integrated circuit having a high punch-through voltage characteristic, a low junction leakage current characteristic and a low polysilicon resistance. In addition, the buried contact junction maintains a relatively low buried contact resistance.

Abstract: A semiconductor apparatus includes multiple protection devices to protect against electrostatic discharge to an internal circuit contained in the semiconductor apparatus. The semiconductor apparatus includes plural terminals including a ground terminal, a substrate bias terminal, a power supply terminal, and an input/output signal terminal. Plural protection devices are connected between various ones of these terminals to provide the necessary discharge protection for a variety of discharge scenarios.

Abstract: The protection device comprises a MOS transistor formed on the substrate of the integrated circuit and connected between a circuit pad and a reference terminal of the integrated circuit. A thyristor formed on the substrate is connected between the pad and the reference terminal. The control electrode of this thyristor consists of a region of the substrate in such a way that the thyristor can be triggerred by a current of charge carriers produced in the substrate by avalanche when a voltage rise occurs between the substrate and the drain of the MOS transistor.

Abstract: A diode structure for protecting a pad in an integrated circuit formed in a P-type substrate coupled between a first supply terminal connected to the substrate and a second supply terminal. The structure includes a P-type pocket whose edges and bottom contact an N-type region, an N-type area formed in the pocket, an N-type ring laterally surrounding the region of the second conductivity type and contacting the substrate, and a P-type well surrounding the ring. The ring and the pocket are connected to the pad, the N-type area formed in the pocket is connected to the second supply terminal and the well is connected to the first supply terminal.

Abstract: In an input/output protection circuit, since the drain of an input protection MOS transistor is directly connected to the cathode of input protection diode and the source and gate of the input protection MOS transistor and the anode of the input protection diode are respectively grounded, an excessive voltage supplied from an external electrode is received by the cathode of the input protection diode and the drain of the input protection MOS transistor before it reaches the internal circuit of a semiconductor device, so that the input/output protection circuit is free from the increase of junction capacitance due to the pattern of the input protection diode. Moreover, when an excessive voltage is input to the device, the input protection diode breaks down prior thereto so as to reduce the voltage at which the input protection MOS transistor starts to conduct. As a result, a high-speed and certain input protection is realized.

Abstract: An integrated structure protection device suitable for protecting a power MOS device from electrostatic discharges comprises a junction diode comprising a first electrode made of a highly doped region of a first conductivity type surrounded by a body region of a second conductivity type and representing a second electrode of the junction diode, which in turn is surrounded by a highly doped deep body region of said second conductivity type. The highly doped region is connected to a polysilicon gate layer representing the gate of the power MOS device, while the deep body region is connected to a source region of the power MOS.

Abstract: A protective circuit protects a plurality of protected portions having different withstand voltages and operation voltages of an active portion of a CCD solid state imaging device or the like by protective elements (e.g., transistors). The respective protected portions can be protected in an optimum fashion in response to the withstand voltages and operation voltages thereof. The breakdown voltages of the respective protective transistors are made different in response to the withstand voltages and operation voltages of the protected portions.

Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors.

Abstract: An electrostatic discharge (ESD) protection device for protecting a high voltage operating circuit having a high voltage input terminal is disclosed. The ESD protection circuit has a substrate, a first diffusion region formed in the substrate connected to the high voltage input terminal, a second diffusion region formed in the substrate connected to ground, a field oxide layer over the substrate having a thickened region extending into the substrate between the first and second diffusion regions, and a drift region formed in the substrate and located between the first diffusion region and the thickened field oxide layer. These regions are so arranged to move the point of avalanche breakdown away from the first diffusion/field oxide interface, so that the avalanche breakdown voltage is lower than that of the protected circuit while simultaneously preventing avalanche included bipolar feedback in the protection device.

Abstract: Multiple punchthru devices are coupled between multiple metal-two conductors and a metal-one bond pad. Each punchthru device has the capacity to couple its respective metal-two conductor to the bond pad when a predetermined voltage potential exists between the metal-two conductor and the bond pad. A set of metal-one islands, one set associated with each metal-one bond pad cell, resides in a bond pad channel. The positioning of the punchthru devices and the islands minimizing the bond pad cell size and minimizing the spacing between adjacent bond pad cells. The bond pad cell configuration also allows any metal-two conductor to be coupled to the bond pad without having to rearrange punchthru devices or reconfigure the bond pad cell. The multiple punchthru devices associated with each bond pad cell provide redundant overvoltage protection superior to present overvoltage protection circuits.

Abstract: A high voltage protection circuit includes a breakdown network for providing a discharge path between a pair of terminal of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other.

Abstract: A semiconductor input protective device has an NPN type blpolar transistor and an N-channel MOS transistor. In the NPN type bipolar transistor, the collector is connected to a signal line and the emitter and the base are commonly connected to a ground line. In the N-channel MOS transistor, either the drain or the source is connected to the signal line and the other of either the drain or the source is connected to the signal line and the gate is connected to either the signal line or the power source line. The N-channel MOS transistor has a threshold voltage higher than the power source voltage. The NPN type bipolar transistor and the N-channel MOS transistor having a thick gate insulation film are used as input protection elements so that, even when a high voltage interface is effected, the function of the protective MOS transistor is not interfered with.

Abstract: The invention is a protection circuit for an integrated circuit which includes an SCR switch, a zener diode in parallel with the SCR to trigger the SCR to its on-state, and a zener diode in series with the SCR controls the on-state or clamping voltage of the SCR. The protection circuit is formed in a semiconductor substrate of first conductivity type having a well region of second conductivity type, a first region of first conductivity type in the well and a second region of second conductivity type in the substrate spaced from the well region. The first region, well region, substrate and second region forming the SCR. A third region of second conductivity type is in the well region and contacts the first region to form a first zener diode. A fourth region of second conductivity type is in the substrate and electrically connected to the well region. A fifth region is in the substrate and contacts the fourth region to form a second zener diode.

Abstract: An ESD protection circuit and structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages. A preferred structure also includes a modification to an N-channel output drive transistor to eliminate the parasitic bipolar transistor that induces snapback.

Abstract: When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.

Abstract: A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).

Abstract: A semiconductor device including a switching device such as a MOSFET or an IGBT, and an avalanche device for protecting the switching device by generating an avalanche current when an overvoltage is applied to the switching device. The avalanche device shares a drift layer, that is, an epitaxial layer with the switching device. With this arrangement, the avalanche voltage of the avalanche device follows changes in the withstanding voltages of the switching device due to variations in the thickness or impurity concentration of the epitaxial layer or temperature. This makes it possible to reduce the margin between the avalanche voltage of the avalanche device and the withstanding voltage of the switching device, and to positively protect the switching device from damage.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

Abstract: A monolithic structure comprises two sets of bidirectional diodes having distinct characteristics constituted from a substrate (1) of a first (N.sup.-) conductivity type. First regions (10, 11, 12) of the second conductivity type constitute the first set of diodes between a first metallization (30) coating one of the first regions and second metallizations (31, 32) coating the other first regions. In a well (15) of the second conductivity type, second regions (20, 21, 22) of the first conductivity type constitute the second set of diodes between a third metallization (40) coating one of the second regions and fourth metallizations (41, 42) coating the other second regions.

Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes. A low breakdown voltage SCR protection circuit is also disclosed.

Abstract: An ESD protection circuit and structure for implementation within an integrated circuit is disclosed. The protection circuit includes a diode, serving as a triggering device, and a lateral bipolar transistor. The triggering voltage of said diode is selected by an implant underlying a first field oxide structure adjacent a first diffused region to which the external terminal is connected. The lateral bipolar transistor uses the first diffused region to which the external terminal is connected as the collector region, a second diffused region opposite the first field oxide structure from said first diffused region as the emitter, and the substrate, or epitaxial layer, as the base. A second field oxide structure encircles the emitter region and has a distance thereacross which is selected in order to provide sufficient base resistance that, upon junction breakdown of the diode, the base-emitter junction of the lateral transistor is forward biased and the transistor turned on.

Abstract: A semiconductor structure (30) is provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Abstract: Disclosed is a MOS transistor with high threshold voltage comprising, in a semiconductor substrate with a first type of conductivity, surface drain and source regions with the second type of conductivity having a high doping concentration, separated by a thick oxide zone in which there is formed, in the substrate, an overdoped region with the first type of conductivity. Each of the drain and source regions is inserted in a well with the second type of conductivity, having a low doping concentration, formed in the substrate.

Abstract: A technique for providing electrostatic discharge (ESD) protection for an open-drain CMOS I/O buffer circuit. having an output terminal. An NMOS enhancement-mode transistor has its drain connected to the VDD power bus for the buffer circuit, its source connected to the output terminal, and its gate connected to a noise-free internal VSS power bus (VSSI). The bulk region is connected to the VSS power bus (VSSE) for the I/O buffer circuit. ESD protection is provided by a parasitic lateral npn bipolar transistor that is inherent to the NMOS transistor. The parasitic lateral npn bipolar transistor has an emitter formed from the drain-to-bulk junction of the NMOS transistor, a collector formed from the source-to-bulk junction of the NMOS transistor, and a base formed in the bulk region.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A circuit for protection from overvoltages of an external electrical connection pad of a circuit integrated in an n type conductivity epitaxial layer formed on a monocrystal semiconductor substrate, comprises a lateral integrated transistor having an emitter connected to said pad, a collector connected to ground and a base connected to said pad across a resistor, and an integrated Zener diode functionally connected between the base and the collector of said transistor.