Abstract: A gate electrode of a field effect transistor is charged during a plasma process, and a gate oxide layer is liable to be damaged; a protective junction diode is connected to the gate electrode of the field effect transistor, and is radiated with light during the plasma process so as to increase leakage current passing through the p-n junction; the leakage current is increased before the breakdown of the protective junction diode so as to prevent the gate oxide layer from the electric charge, and the breakdown voltage is higher than a test voltage applied to the gate electrode during a diagnosis on the gate oxide layer so that the manufacturer exactly diagnoses the semiconductor device.

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: When an element of an internal circuit is arranged in the vicinity of an input/output terminal of an LSI chip, electrostatic break down is caused in an internal circuit element by discharge current generated between an input/output terminal and a grounding terminal or a power source terminal. Therefore, the elements are arranged with a distance to cause dead space therebetween to make down-sizing of the LSI chip difficult. Therefore, a resistor is disposed between an input/output terminal and a protection element connected thereto. The resistor causes increasing of resistance of a current path from the input/output terminal to the grounding terminal, at the common wiring. Thus influence of the electrostatic break down for the element of the internal circuit can be restricted to permit location of the resistor to permit the internal circuit element to be arranged in the vicinity of the protection element of the input/output terminal.

Abstract: A protection circuit (1) for input comprises two transistors (11, 12) connected in series between a first voltage supply (V.sub.cc) and a second voltage supply (GND), and an intermediate junction point is used as an input terminal and an output terminal. When a surge voltage is applied to the input terminal, since terminals (51, 53) of the two transistors (11, 12) are connected to predetermined junction points in such a way that the transistors can operate as bipolar transistors or cause punch through phenomenon (without causing breakdown operation of a low response speed to surge voltage), the surge voltage can be absorbed at high speed, thus increasing anti-ESD (electro static discharge) rate. Further, a protection circuit for power supply comprises two transistors (31, 32) connected in parallel to each other between a first voltage supply (V.sub.cc) and a second voltage supply (GND).

Abstract: An ESD protection network (20) provides energy discharge paths for an ESD event at an external circuit port (42). The paths include one portion (28) into an integrated circuit substrate (72) and other portions (29, 30) from the substrate to external power supply ports (43, 44). In particular, these paths include energy discharge routes around on-circuit voltage sources.

Abstract: An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and

Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped re

Abstract: A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a specific conductivity type, also used for the heavily doped source and drain regions of attached FET devices. After photoresist processing, used to mask the attached FET devices, a second ion implantation step, opposite in conductivity type then the first implant, is used to complete the ESD protection diode, for the ESD protection device. This large area diode reduces junction breakdown voltage, while allowing ESD current to be discharged more efficiently then for smaller ESD protection counterparts.

Abstract: A device for protecting an integrated circuit against electrostatic discharges, and adapted for connection between a terminal and a ground of the integrated circuit, which includes a first transistor (Q2) connected between that terminal and ground by its emitter terminal and collector terminal, respectively, and a second transistor (Q1) which has its base terminal connected to the base terminal of the first transistor. The emitter and collector terminals of the second transistor (Q2) are connected to the collector of the first transistor (Q1).

Abstract: An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the drain cylindrical edge. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

Abstract: The present invention provides a silicon on insulator type semiconductor device including a transistor, a diode and a power source line. The transistor includes an insulator, a silicon film with which the insulator is selectively covered to form a device formation region, a gate insulating film with which the device formation region is covered, a gate electrode formed on the gate insulating film, a region having first conductivity and formed in the silicon film below the gate electrode across the gate insulating film, and source and drain regions both having second conductivity and formed in the silicon film in self-aligned fashion about the gate electrode so that the region is sandwiched between the source and drain regions. The diode is in electrical connection with the transistor through the drain region. Both the diode and the source region of the transistor are electrically connected to the power source line.

Abstract: A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including; a semiconductor substrate; an epitaxial layer laminated on the semiconductor substrate; a buried collector of a first conductivity type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer; a base of a second conductivity type which is a lightly doped well and formed on the epitaxial layer; and an emitter of the first conductivity type and formed on the surface layer of the base of the second conductivity type; and in which the base is adapted to have impurity concentration and depth so that a punch-through is generated between the emitter and the collector of the electrostatic discharge protection dev

Abstract: Protecting device structures are disclosed for protecting one or more protected nodes of an integrated circuit to be protected against electrostatic discharges (ESD). Typically the integrated circuit includes n channel MOS transistors having terminals connected to the protected nodes. In a specific embodiment, the protecting device structure includes an MOS diode structure having source and drain regions and at least a pair of localized auxiliary region. Each of this pair of localized auxiliary regions has a conductivity type that is opposite from that of the source and drain regions. These localized auxiliary regions are located contiguous with the source and drain regions, respectively, and in the channel between the source and drain regions. The protecting device structure is integrated in the integrated circuit and has a terminal that is connected to a terminal of each of the one or more protected nodes of the integrated circuit.

Abstract: An electrostatic discharge (ESD) protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, and which includes an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit driven by the transient detection circuit and connected between the VDD and VSS lines, wherein the discharge circuit includes a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein the bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein the bipolar transistor has a base that is driven by the transient detection circuit.

Abstract: A punchthrough-triggered ESD protection circuit which disposes an NMOS transistor at the anode gate of an lateral silicon-controlled rectifier, and a control circuit which provides a gate voltage for the gate of the NMOS transistor. By changing the channel length of the NMOS transistor as well as the gate voltage, the punchthrough voltage of the NMOS transistor is readily adjusted to a predetermined level. When ESD stress is present at the IC pad, the NMOS transistor goes into breakdown because of punchthrough and then triggers on the lateral silicon controlled rectifier. Thus, the trigger voltage of the ESD voltage can be lowered to the punchthrough voltage of the NMOS transistor. Accordingly, the ESD stress at the IC pad is bypassed by the conduction of the ESD protection circuit to allow an internal circuit to be protected from ESD damage.

Abstract: A semiconductor device with a semiconductor body (3) including a surface region (5) of a first conductivity type which adjoins a surface (4) and in which a field effect transistor (1) with insulated gate (6) is provided. The field effect transistor (1) has source and drain regions (7, 8, respectively) of the second, opposed conductivity type situated in the surface region (5), and a channel region (9) of the first conductivity type situated between the source and drain regions. A metal gate electrode (6) separated from the channel region (9) by an insulating layer (10) is provided over the channel region (9) and is provided with a protection device (2) against excessive voltages applied to the gate electrode (6).

Abstract: A semiconductor device includes a metallic main line connected between an external terminal and an internal circuit, and a plurality of divided protection bipolar transistors connected in parallel to one another. Each of the divided protection bipolar transistors includes a collector and an emitter composed of first and second N diffused regions formed in a semiconductor substrate which are separated from each other. Each of the divided protection bipolar transistors also includes a base formed of a portion of a semiconductor substrate between the collector and the emitter. The collector is connected to a metallic sub line branched from the main line, and the emitter is connected to ground. The plurality of divided protection bipolar transistors have an equal breakdown voltage between the collector of the divided protection bipolar transistor and the semiconductor substrate.

Abstract: A protection structure and method are provided for protecting a first pad of an integrated circuit, the integrated circuit having a second pad to receive a first supply voltage. The protection structure includes a first region of a first conductivity type coupled to the first pad; a second region of a second conductivity type coupled to the second pad; a substrate of the second conductivity type contacting the first and second regions; and an epitaxial layer of the first conductivity type. The epitaxial layer has an epitaxial region that contacts the first and second regions. A first diode can be formed outside the substrate between the first and second pads through at least two of the first region, the second region, and the epitaxial region. The protection structure may include a first portion and a second portion, wherein each portion has a different voltage threshold. Accordingly, the first diode can be formed through the second portion, but not the first portion.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.

Abstract: An input protection circuit comprises an internal circuit and an input terminal, between which a pair of rectifying devices are interposed with polygonal diffusion regions of one and the other conduction types, which diffusion regions are formed longer along the width thereof orthogonal to the direction of current flow in the wiring than along the direction of current flow. The width of the contacts between said wiring and said diffusion regions is greater than the width of the wiring not having the contacts, thereby achieving a high electrostatic breakdown voltage.

Abstract: A protective circuit for a semiconductor integrated circuit having a MOS transistor is constructed of a protective device having a first conducting type of protective device region provided in the surface of a substrate and a second conducting type of first diffused part and second diffused part provided in the surface of the protective device region. The first diffused part is connected to a power line of the MOS transistor, and the second diffused part is connected to a signal line between an external input terminal and the MOS transistor. The bipolar operation of the protective device allows electric charge accumulated in the power line to be discharged from the external input terminal, and also allows electric charge accumulated in the external input terminal to be discharged from the power line. Accordingly, the occurrence of electrostatic breakdown in the semiconductor integrated circuit can be prevented.

Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.

Abstract: A semiconductor device having a surge input detecting circuit is provided with the driving circuit for, for example, reversible motor. To prevent MOS power transistors constituting the power driving circuit from their destructive breakdowns (failures), when the surge input detecting circuit block detects the surge voltage input through the driving circuit which exceeds a predetermined voltage, namely, a maximum rated power supply voltage of the power driving circuit, the surge input detecting circuit outputs the signal to turn the MOS power transistors in off-states. These circuit elements are integrally mounted on a semiconductor chip. The surge input detecting circuit block detects such a surge input through a power supply terminal in terms of either of its voltage, its current, or the temperature rise in the semiconductor chip. The breakdown voltage per power transistor can be half the maximum rated power supply voltage.

Abstract: A configuration for protecting a first semiconductor component being controllable by field effect against electrostatic discharges, includes a voltage-limiting, protective, second semiconductor component being connected to the gate terminal of the first semiconductor component. The second semiconductor component is an integrated bipolar transistor having a collector-to-emitter path being connected between the drain terminal and the gate terminal of the first semiconductor component.

Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Abstract: An input protection device comprises a current limiting resistor externally connected to an integrated circuit which includes two Zener diodes, one functioning as a power supply Zener diode and the other functioning as a ground Zener diode. Owing to the resistance of the current limiting resistor and junction capacitances of the Zener diodes, electromagnetic interference noise is effectively damped or attenuated.

Abstract: An integrated structure protection circuit suitable for protecting a power device against overvoltages comprises a plurality of serially connected junction diodes, each having a first electrode, represented by a highly doped region of a first conductivity type, and a second electrode represented by a medium doped or low doped region of a second conductivity type. A first diode of said plurality has its first electrode connected to a gate layer of said power device and its second electrode connected to the second electrode of at least one second diode of said plurality, and said at least one second diode has its first electrode connected to a drain region of the power device. The doping level of the second electrode of the diodes of said plurality is suitable to achieve sufficiently high breakdown voltage values.

Abstract: A diode structure for protecting a pad in an integrated circuit formed in a P-type substrate coupled between a first supply terminal connected to the substrate and a second supply terminal. The structure includes a P-type pocket whose edges and bottom contact an N-type region, an N-type area formed in the pocket, an N-type ring laterally surrounding the region of the second conductivity type and contacting the substrate, and a P-type well surrounding the ring. The ring and the pocket are connected to the pad, the N-type area formed in the pocket is connected to the second supply terminal and the well is connected to the first supply terminal.

Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors. The protection circuit is designed to prevent an excess signal supplied on the signal line from damaging the semiconductor apparatus, such as by breaking down a dielectric layer formed at a gate of a MOS transistor. The protection circuit may further be connected to a potential line that is connected to an external source of voltage.

Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.

Abstract: An ESD protection circuit fully protects the input stage of CMOS integrated circuits from four different ESD stress modes by providing four different ESD direct discharging paths. The ESD protection circuit has a primary ESD protection circuit, which has a first and a second thick-oxide MOS devices, and a secondary ESD protection circuit which has a resistor, a first and a second thin-oxide MOS devices. The resistor is connected between the primary and secondary ESD protection circuits. The primary and secondary ESD protection circuits each provide two ESD discharge paths from the input pad, and from the input of the internal circuits to be protected, to VDD and VSS voltage supply buses. The inventive ESD protection circuit also has merged latchup guard rings and protects against large ESDs, while occupying only a small layout area. Furthermore, the inventive ESD protection circuit clamps the voltage level of the input signal between 5.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V.sub.DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

Abstract: A semiconductor component for switching an inductive load, comprises first and second external terminals, first and second control terminals and a node. A vertical bipolar transistor has a base region and is disposed between the first external terminal and the node. A first vertical transistor is disposed between the node and the second external terminal. A zener diode and a second vertical transistor are connected parallel between the base and the node.

Abstract: An electrostatic protection device for use in a semiconductor integrated circuit, includes a base region of a first conductivity type formed at a principal surface of a semiconductor substrate, a plurality of collector regions constituted of a plurality of first diffused regions of a second conductivity type opposite to the first conductivity type. The first diffused regions are formed on a surface of the base region in the form of a plurality of strips parallel to each other but separate from each other. Emitter regions are constituted of a second diffused region of the second conductivity type formed in the form of a strip between each pair of adjacent collector regions of the plurality of collector regions and a third diffused region of the second conductivity type formed under a contact hole formed in at least one portion of a boundary region at a side of the second diffused region adjacent to the collector region, the third diffused region being connected to the second diffused region.

Abstract: An electrical overstress (EOS) protection circuit includes a pair of contra-directed diode-connected bipolar EOS transistors connected between two integrated circuit (IC) terminals. One of the EOS transistors has a reverse-biased junction and the other has a forward-biased junction when a voltage is applied across the IC terminals. A pair of parasitic bipolar transistors are formed in series to provide a current path between the EOS transistors. When the voltage difference between the IC terminals exceeds the breakdown voltage of the EOS transistor with a reverse-biased junction as during an electrostatic discharge event, the parasitic transistors activate the EOS transistor with a reverse-biased junction to divert ESD current from the IC.

Abstract: According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt excess current away from sensitive regions with even current distribution for minimal damage. In order to improve the ESD immunity of the positive going ESD with respect to V.sub.SS, the reverse bias breakdowns of the diode and of the transistor's functioning as a collector/base diode are reduced. This circuit provides a simple low cost approach for improving ESD protection, in a process which fits into most standard Cmos process flows with few or no added process steps.

Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.

Abstract: To reduce the required diffusion depth of impurities in manufacturing a protective diode for protecting an insulated gate transistor from overvoltage so that the diode can be easily built in a chip of the transistor. A plurality of p-type diode layers are built in by diffusion through the windows in an insulation film disposed on an n-type region into which a depletion layers spread when the vertical field effect transistor to be protected is turned off, and a diode terminal A is led out from an electrode film that is in electrical contact with the diode layers. This configuration prevents depletion layers, spreading from the diode layers into the semiconductor region by the applied overvoltage, from joining with each other, and sufficiently lowers the breakdown voltage of the protective diode with respect to the withstand voltage of the transistor 10 or 20 even when the diffusion depth of the diode layer is one order of magnitude shallower than in conventional devices.

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.

Abstract: An ESD protection device is disclosed having a first region of a first conductivity type. A second region, which is heavily doped, of a second conductivity type is disposed in the first region. The second region extends from the surface of the first region a first depth. A third region, which is heavily doped, of the second conductivity type, is also disposed in the first region such that the third region is separated from the second region by a portion of the surface of the first region. The third region extends from the surface of the first region a second depth less than the first depth of the second region. An insulating region is grown on a portion of the surface of the first region between the second and third regions. Furthermore, a resistive conducting region is disposed on the second region and the insulating region. A portion of the resistive conducting region extends beyond the second region for receiving an input signal.