Abstract: A transient protection circuit (14) includes a resistor (22) having a first end adapted for connection to a first signal line (16) of a voltage supply (12) and a second opposite end connected to a voltage supply input (20) of an application circuit (18). In one embodiment, the resistor (22) defines an emitter (26) of a PNP transistor (24) having a floating base (28) and a collector (30) adapted for connection to a reference signal line (15) of the voltage supply (12). In an alternative embodiment (14′), the emitter (26) of the PNP transistor (24) is connected to the first end of the resistor (22). The transient protection circuit (14, 14′) is preferably formed on a monolithic integrated circuit including the application circuit (18) wherein a semiconductor layer (46) defining the first input to the resistor (22) also defines a bond pad (50).

Abstract: A semiconductor integrated circuit device for a magnetic drive apparatus has a driver for supplying an electric current to a motor including an inductance coil, a pad for receiving or outputting a signal from or to outside, and a protection diode connected to the pad. In this semiconductor integrated circuit device, the pad is disposed near the driver, and the protection diode is disposed at a predetermined distance from the driver.

Abstract: An apparatus includes a first doped region, a first doped well, a first doped plug, a second doped plug, and an isolation structure. The first doped well is disposed within the first doped region. The first doped plug is disposed within the first doped well. The second doped plug is disposed within the first doped region. The isolation structure is disposed between the first and second doped plugs. A method includes providing a first doped region. A first doped well is formed within the first doped region, and a first doped plug is formed within the first doped well. A second doped plug is formed within the first doped region, and an isolation structure is formed between the first and second doped plugs.

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p−, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (=Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD.

Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

Abstract: The invention relates to a SOI deep depletion MOS transistor provided in a thin silicon layer (5) adjoining a surface (4) of a silicon body (3) and insulated from a silicon substrate (7) by a buried oxide layer (6). The channel region (13) of a first conductivity type is provided with at least one and preferably a plurality of zones (16) of the opposite conductivity type adjoining the surface to remove minority carriers from the interface between the channel and the gate oxide (15). The zones (16) extend across the whole thickness of the channel and adjoin the buried oxide at the side of the channel remote from the gate dielectric. Due to this construction, minority carriers are removed also from the rear side of the channel. This enables the transistor to be operative also at high voltages having values at which the substrate and the buried oxide operate as a second gate and as a second gate dielectric, respectively.

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

Abstract: An SCR with a high trigger current is provided in a P-type semiconductor substrate with an N-well formed therein. In the P-type semiconductor substrate, there is provided a P-type region and an N-type region. In the N-well, there is provided another P-type region and another N-well. The P-type region and the N-type region in the P-type region as well as another P-type region formed between the P-type semiconductor substrate and the N-well are connected to serve as a cathode of the SCR circuit, while the P-type region and the N-type region in the N-well are connected to serve as an anode of the SCR circuit. In addition, the anode can be formed only using a P-type region, and the cathode can be formed only using an N-type region.

Abstract: On one side of a shallow trench isolation region formed on the surface of a p type well, an n type source region is provided while on the other side thereof, an n type drain region is provided so as to sandwich the shallow trench isolation region. In the drain region, a bent portion to allow a breakdown current to flow is provided and connected to a gate of a MOSFET comprising a circuit to be protected. Furthermore, a well contact connected to the source region is formed on the well surface and this well contact is grounded. When a positive high voltage which is higher than a predetermine voltage is applied to the drain region, since electric fields concentrate at the bent portion, a breakdown current flows from this bent portion toward the well contact. Thereafter, a current flows between the source and the drain.

Abstract: An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node.

Abstract: In accordance with the present invention, a semiconductor integrated circuit comprises an internal circuit, an output driver circuit connected to the internal circuit for amplifying an output signal from the output driver circuit to output an amplified output signal, at least a first electrode pad connected to the output driver circuit for receipt of the amplified output signal from the output driver circuit, a first ground line connected to the internal circuit for supplying a ground potential to the internal circuit and a second ground line connected to the output driver circuit for supplying the ground potential to the output driver circuit, wherein at least an electrostatic discharge protection circuit is provided between the first electrode pad and the second ground line.

Abstract: An integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The internal integrated circuit is conductively coupled to the integrated circuit pad so as to define a primary electrical path from the integrated circuit pad to the internal integrated circuit. The ESD protection circuit is conductively coupled to the integrated circuit pad so as to define a secondary electrical path from the integrated circuit pad to the ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The drain region is formed in the silicon substrate and is conductively coupled to the integrated circuit pad via the secondary electrical path. The source region is formed in the silicon substrate and is conductively coupled to a relatively low electrical potential.

Abstract: A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled with polysilicon; a gate conductor formed over the trench region; and source/drain regions formed within the well region laterally aligned to the gate conductor. A suitable method to form the MOS transistor includes the acts of: forming a well region in a semiconductor substrate; forming a trench region in the well region; forming an isolator in a corner of the trench region; filling the trench region with polysilicon; forming a gate conductor formed over the trench region; and forming source/drain regions within the well region on opposite sides of the gate conductor.

Abstract: An integrated semiconductor circuit has a protection structure for protecting against electrostatic discharge. The protection element has at least one integrated vertical protection transistor, whose load path is connected between the terminal pad and a potential rail. The base of the vertical npn bipolar transistor is controlled by a diode at breakdown, whose breakdown voltage is above the holding voltage of the npn bipolar transistors. By suitably choosing the location of the base contact, of the pn junction of the breakdown diode, and of the emitter, a desired adjustment of the trigger current is possible. Thus a variation in the voltage drop at the base is achieved which enables a current flow. The signal voltage requirements can be met and at the same time, an optimization of the ESD strength is achieved. The control or trigger sensitivity of the base can also be adjusted by means of an integrated resistor, which is disposed in the base zone.

Abstract: A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base.

Abstract: In order to reduce the amplitude of an overshoot/undershoot voltage and clamp a signal at a constant voltage level over a wide temperature range, a bias voltage having a clamping element operating at a boundary region between ON and OFF states is applied to a control electrode node of the damping element. When the difference between the voltage of a signal line and the bias voltage is higher than a P-N junction built-in voltage, the clamping element is rendered conductive to clamp the overshoot/undershoot voltage.

Abstract: In a semiconductor device, in order to protect an interior of the device, protective circuits are provided. The protective circuits include a first circuit connected between the first terminal and a negative potential line, a second circuit connected between the first terminal and a ground potential line, and a third circuit connected between the ground potential line and a second terminal. The first circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the negative potential line, and a gate connected with the first terminal or the negative potential line. The second circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the ground potential line, and a gate connected with the first terminal or the ground potential line.

Abstract: A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p.sup.+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p.sup.+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n.sup.+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.

Abstract: A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first terminal of the electronic circuit to receive a supply voltage, and a second terminal of the electronic circuit to receive a second reference potential. The transistors are connected together to form an output terminal of the electronic circuit for connection to an external load. The pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate.

Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.

Abstract: A structure of manufacturing an electrostatic discharge protective circuit for SRAM. In the structure, a MOS transistor is coupled between an input port and an internal circuit, and an input bonding pad is coupled to the input port and the internal circuit. Furthermore, the source of the MOS transistor is connected to the gate of the MOS transistor by a polysilicon layer which is coupled to a potential line. A via connects the drain of the MOS transistor to a metal layer. Then, the metal layer is coupled to the input bonding pad.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.OE17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 .mu.m. The thickness of the third (p+) region should be between about 0.3 .mu.m and about 2.0 .mu.m, and the thickness of the second (p-) region should be between about 0.5 .mu.m and about 5.0 .

Abstract: A semiconductor device provided with a planar bipolar transistor and a built-in ingredient acting as an element to protect the bipolar transistor from an external surge voltage e.g. an electrostatic surge voltage and the like, is provided with a planar bipolar transistor further provided with a doped region having a conductivity opposite to that of a semiconductor substrate in which the foregoing planar bipolar transistor is produced, the doped region being produced along the top surface of the semiconductor substrate at a location close to the bipolar transistor, and the emitter of the bipolar transistor being connected the doped region and a fixed potential (V.sub.EE) or the ground potential, whereby the operation speed of a circuit including the transistor is not reduced by potential parasitic capacitors which otherwise accompany the built-in ingredients produced to protect the transistor from an external surge voltage e.g. an electrostatic surge voltage and the like.

Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Abstract: A semiconductor device having a zener diode, wherein an anode electrode and a cathode electrode of the zener diode have a barrier metal layer as an underlying layer, i.e., a barrier metal structure to simplify manufacturing steps of the semiconductor device, while ensuring that the zener diode is short-circuited with a low resistance without variations in resistance. The anode electrode (6) and the cathode electrode (8) are formed with an underlying metal layer made of a barrier metal. The anode electrode and the cathode electrode are shaped such that Xa<La and Xc<Lc are satisfied, where Xa and Xc are the widths of opposite sides of contact portions of the anode electrode and the cathode electrode, at which they are connected to an anode region and a cathode region, respectively, and La and Lc are the lengths of the respective contact portions.

Abstract: A new method of fabricating a new vertical bipolar transistor in a protection circuit is disclosed. In the disclosed system, a layer of gate electrode material is formed over a selected surface of a silicon wafer. The gate electrode material is patterned to form gates between an emitter stripe and a base contact within the bipolar transistor. In an example embodiment, the gate as well as the emitter stripe are coupled with an input source such that excess voltage is limited and excess current sunk during ESD events on the input source. A conductive channel under the gate is formed in the presence of an ESD event on the input source. The channel conductance may further be enhanced by introduction of an appropriate dopant material. Sidewall spacers may be formed adjacent to the base/emitter isolation regions. Where the bipolar transistor is a PNP transistor, a light dosage of an n-type dopant may be implanted into the base contact prior to forming the sidewall spacers.

Abstract: The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region.

Abstract: In the manufacture of integrated circuits, damage to transistors caused by ESD is customarily precluded by connecting the gates of the transistors, in an early stage, to a protection diode. If, for example during plasma etching or reactive ion etching, an electric charge is stored on a floating gate, this charge can be removed via the diode before electric breakdown occurs. In a first embodiment of a device in accordance with the invention, the diode is formed in an active region covered by an electrically insulating layer 12. The gate 8, or a poly track 9 connected thereto, projects above this layer and covers only a part of the active region. In the uncovered part of the active region, a cathode or anode is provided so as to be self-aligned relative to the poly track. In another embodiment, the poly track 9 is situated directly next to the region of the diode. The poly track 9 and the surface zone 10 of the protection diode are interconnected by an overlapping metal contact 15.

Abstract: A semiconductor memory device is provided for preventing loss of cell data and reduction of a standby current. The semiconductor memory device includes a first conductivity type semiconductor substrate connected to a ground voltage, a first well region of second conductivity type formed over the semiconductor substrate and connected to the ground voltage, a second well region of the first conductivity type embedded in the first well region, a first impurity region of the second conductivity type embedded in the second well region and connected to an input/output pad, and one or more additional impurity regions embedded in the second well region separately from the first impurity region, the one or more additional impurity regions being connected to the ground voltage.

Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

Abstract: The device has an SCR structure in a P surface zone of a silicon die. A P+ anode region for connection to an I/O terminal to be protected is formed in an N region, as well as an N+ contact region; an N+ cathode region is formed in another N region for connection to the earth of the integrated circuit. The striking potential of the SCR, that is, the intervention potential of the protection device, is determined by the reverse breakdown of the junction between the first N region and the P-body surface zone. This potential is influenced by an electrode which is disposed over the junction and is connected to the cathode constituting the gate of a cut-off N-channel MOS transistor. The concentrations are selected in a manner such that the P-channel MOS transistor defined by the P region, by the portion of the first region over which the electrode is disposed, and by the P-body, has a conduction threshold greater than the striking potential.

Abstract: A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body electrically coupled to the base. A reverse-bias at the emitter-base junction, which is less than a breakdown voltage for the emitter-base junction, activates the MOS transistor which substantially reduces the resistance between the emitter and the base. Preferably, a first semiconductor region provides both the drain and the emitter, and a second semiconductor region provides both the body and the base, for reduced surface area on an integrated circuit chip.

Abstract: According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: The present invention provides an electrostatic breakdown protecting device which has a high electrostatic breakdown resistance, a high latch up resistance and an excellent protective ability and which has no dead space in the vicinity of protective elements. The present invention includes an I/O terminal directly connected to a protective diode comprising a p-type diffusion layer 103a and an n-type diffusion layer 102b, and an NPN protective bipolar transistor comprising n-type diffusion layers 102b, 102c and a p-type well 113 and connected to an NMOSFET for protection comprising n-type diffusion layers 102c, 102d and a gate electrode 105 via an input resistor 114. These protective elements are formed on the p-type well 113 separated from a substrate for an internal circuit by an n-type buried diffusion layer 111 and an n-type well 112. The internal circuit to be protected is connected to a drain 102d of the NMOSFET for protection.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Abstract: A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base.

Abstract: A self-aligned protection diode is formed at the first polycrystalline silicon level, thereby enabling in-process charging damage protection while reducing the layout area. The self-aligned protection diode is formed by providing an etch stop layer having an arcuate portion with different etching characteristics than horizontal portions, isotropically etching the arcuate portion to form a through hole exposing a side surface of a polycrystalline silicon layer and the underlying semiconductor substrate, ion implanting impurities to form the protection diode, and filling the through hole with a metal interconnecting the side surface of the polycrystalline silicon layer with the vertically self-aligned protection diode.

Abstract: An integrated circuit formed on a semiconductor substrate has a contact pad for communicating signals between an external device and an internal signal line. The pad is protected by an SCR that conducts electrostatic discharge pulses from the pad directly to a current sink. The SCR includes a subregion underneath a field oxide that has a field inplant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that SCR triggers before an ESD pulse can cause latch-up or damage in other devices in the integrated circuit.

Abstract: An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

Abstract: In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantageously used to protect MOS type integrated circuits against electrical discharges.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract: An Electric Static Discharge (ESD) protection network for nonvolatile memory using a high voltage dual thin oxide MOSFET. In one aspect, there is a dual oxide electric static discharge (ESD) protective network for nonvolatile memory in which ESD protection is provided using a thick oxide PFET in a thick epitaxial layer with sequence independent circuitry. The dual oxide ESD network includes a high voltage PFET ESD network for 12 V to 5 V applications as well as a low voltage PFET network 5 V to 3 V applications taking advantage of dual oxides supported by the disclosed technology. The circuit saves space, is migratable, improves reliability, and it is voltage differential independent.

Abstract: An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises a PNP transistor, a NPN transistor, and an erasable programmable read only memory. The PNP and NPN transistors have an emitter, a base, and a collector, respectively. The PNP transistor is configured with its emitter connected to the pad, its base connected to the collector of the NPN transistor, and its collector connected to the base of the NPN transistor. The emitter of the NPN transistor is connected to a circuit node. The erasable programmable read only memory is configured with a drain connected to the base of the PNP transistor, a source connected to the circuit node, and a control gate coupled to the circuit node. When electrostatic discharge stress occurs at the pad, the erasable programmable read only memory enters breakdown to be programmed and triggers the conduction of the transistors.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.