Including Resistor Element Patents (Class 257/363)
  • Patent number: 10756029
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 25, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Patent number: 10720395
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Patent number: 10566967
    Abstract: A circuit arrangement for driving an inductive load is connectable to a load terminal. A first MOS field effect transistor is connected between a terminal for a high potential of a first supply voltage source and the load terminal. A series connection with a freewheeling diode and a second MOS field effect transistor has its freewheeling diode connected between the load terminal and a second terminal for a low potential of the first supply voltage source. The freewheeling diode has its cathode connected to the load terminal. A series connection with a reverse-biased zener diode and a forward-biased diode is connected between the drain and gate terminals of the first MOS field effect transistor. A first control signal terminal is connected to the gate terminal of the second MOS field effect transistor and via an AND circuit to the gate terminal of the first MOS field effect transistor.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: February 18, 2020
    Assignee: Continental Automotive GmbH
    Inventors: Zoltan Csoka, Octavian Luca
  • Patent number: 10490109
    Abstract: An array substrate, a testing method and a manufacturing method of the array substrate are disclosed. The array substrate comprises a first test line (3), a second test line (4), and first data lines (1) and second data lines (2) that are disposed alternately. The first data lines (1) are directly connected to the first test line (3), and the second data lines (2) are connected to the second test line (4) through switch elements (7); or, the second data lines (2) are directly connected to the second test line (4), and the first data lines (1) are connected to the first test line (3) through switch elements (7). With the array substrate, charges in the display region can be avoided from being transferred to a test line, thereby decreasing the accumulation of static electricity, and enhancing reliability of the short bar region.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Liangliang Li, Zongjie Guo, Xiangqian Ding, Yao Liu, Jinchao Bai
  • Patent number: 10361557
    Abstract: A semiconductor device that can hold ESD immunity with a simple configuration is provided. The semiconductor device includes a power supply wiring, a ground wiring, an input circuit coupled between the power supply wiring and the ground wiring, an input pad which is coupled with the input circuit and to which a negative voltage lower than a voltage supplied to the ground wiring can be inputted, a plurality of first diodes provided between the ground wiring and the input pad, and a second diode provided between the input pad and the power supply wiring. A reverse bias breakdown voltage of the second diode is greater than a reverse bias breakdown voltage of each of the first diodes.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masanori Tanaka
  • Patent number: 10342107
    Abstract: An apparatus is provided including a cascaded transformer set and a voltage divider. The cascaded transformer set includes a plurality of transformers, each having a primary and a secondary winding. The secondary winding of one transformer feeds the primary winding of an adjacent transformer. The voltage divider includes a plurality of capacitors and a plurality of resistors configured to divide a voltage applied to the cascaded transformer set among the plurality of transformers. The capacitors of the voltage divider may include a series of disks that are also used in the support structure of the apparatus.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 2, 2019
    Assignee: KIMTRON, INC.
    Inventor: John Matilaine
  • Patent number: 9991329
    Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 5, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Patent number: 9590520
    Abstract: A power control circuit includes a solid state power controller operable to connect an AC power source to a load. The solid state power controller includes a first switching device and a second switching device arranged serially. Each of the switching devices includes a diode, a controller controllably coupled to each of the first switching device and the second switching device, such that the controller is capable of controlling an on/off state of the first switching device and the second switching device. The controller further includes a non-transitory memory storing instructions for causing the controller to perform the steps of: switching off a first switching device having a diode aligned with a current polarity of an AC current flow prior to a first zero crossing, delaying a switching off of a second switching device until after the first zero crossing, and switching the second switching device off after the delay and before a second zero crossing.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 7, 2017
    Assignee: Hamilton Sundstrand Corporation
    Inventor: John A. Dickey
  • Patent number: 9494833
    Abstract: To provide a display device with little signal delay and a display device that can operate with low power consumption, parasitic capacitance between a common wiring that applies a common potential to a plurality of pixels and signal lines that input signals for driving the pixels is avoided. Specifically, the common wiring is routed outwardly with respect to an external input terminal to which a signal is input from the, outside, to avoid intersections of the signal lines and the common wiring. Thus, parasitic capacitance between the common wiring and the signal lines is avoided, so that the display device can operate at high speed with low power consumption.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 9401257
    Abstract: A circuit protection device includes a conductive layer which is connected to first and second terminals. A spring is electrically connected to the first and second terminals. When an over-voltage or over-temperature condition occurs within a charging circuit, one or more heat generating resistive elements melts material associated with one or more of the ends of the spring thereby releasing the spring to create an open circuit.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 26, 2016
    Assignee: LITTELFUSE, INC.
    Inventors: G. Todd Dietsch, Olga Spaldon-Stewart, Stephen Whitney
  • Patent number: 9305929
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita A. Chavan
  • Patent number: 9299612
    Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 9012291
    Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 21, 2015
    Assignee: Tsinghua University
    Inventors: Yu-dong Wang, Jun Fu, Jie Cui, Yue Zhao, Zhi-hong Liu, Wei Zhang, Gao-qing Li, Zheng-li Wu, Ping Xu
  • Patent number: 9006838
    Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Rajni J. Aggarwal, Jau-Yuann Yang
  • Patent number: 8981484
    Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Patent number: 8963277
    Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8928043
    Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 6, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Patent number: 8847320
    Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • Patent number: 8816436
    Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8686478
    Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Benjamin T. Voegeli, Kimball M. Watson
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Publication number: 20140054708
    Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.
    Type: Application
    Filed: November 4, 2013
    Publication date: February 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8618608
    Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 31, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ta-Cheng Lin, Te-Chang Wu
  • Patent number: 8592910
    Abstract: A semiconductor body includes a protective structure. The protective structure (10) includes a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure includes an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 26, 2013
    Assignee: AMS AG
    Inventor: Hubert Enichlmair
  • Patent number: 8525265
    Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 3, 2013
    Assignees: United Microelectronics Corp., National Chiao Tung University
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Patent number: 8513738
    Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: John B. Campi, Jr., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
  • Patent number: 8462251
    Abstract: A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: June 11, 2013
    Assignee: Renesas Technology Corp.
    Inventor: Hiroki Shimano
  • Patent number: 8368145
    Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Patent number: 8357976
    Abstract: An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher L. Rexer, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun
  • Patent number: 8334572
    Abstract: A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang
  • Patent number: 8310011
    Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 13, 2012
    Assignee: GlobalFoundries Inc.
    Inventors: Akram A. Salman, Stephen G. Beebe, Shuqing Cao
  • Patent number: 8283729
    Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 9, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Publication number: 20120132995
    Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8143674
    Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Sang-Yoon Kim
  • Patent number: 8102002
    Abstract: The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: January 24, 2012
    Assignee: Analog Devices, Inc.
    Inventors: David Foley, Haiyang Zhu
  • Publication number: 20110303982
    Abstract: A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang
  • Patent number: 8018002
    Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: September 13, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Akram A. Salman, Stephen G. Beebe, Shuqing Cao
  • Patent number: 8010927
    Abstract: Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 7999324
    Abstract: A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoyuki Shigyo, Kentaro Watanabe
  • Patent number: 7986007
    Abstract: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: July 26, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yi Huang, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Patent number: 7948036
    Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: May 24, 2011
    Assignee: LSI Corporation
    Inventor: Jau-Wen Chen
  • Patent number: 7923783
    Abstract: A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takumi Abe
  • Patent number: 7919821
    Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: April 5, 2011
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yan-Nan Li, Hsueh-Li Chiang
  • Patent number: 7898035
    Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 1, 2011
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Sukehiro Yamamoto
  • Patent number: 7893497
    Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 22, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 7888739
    Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-hee Jeon, Han-gu Kim, Sung-pil Jang
  • Patent number: 7871890
    Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: January 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Sang-Yoon Kim
  • Patent number: 7859057
    Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: December 28, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher L. Rexer, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun
  • Patent number: RE42776
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do
  • Patent number: RE47817
    Abstract: An object of the present invention is to provide a display device capable of narrowing the area of the frame. In order to achieve this object, the display device according to the present invention has a substrate having a plurality of arranged display elements and a wiring layer of a power source on the peripheral side; a bank layer for mutually separating the display elements; an electrode layer for covering the plurality of display elements and the bank layer; and a sealing substrate for further covering the electrode layer by joining the peripheral portion of the substrate and the sealing portion circling around the periphery via a joining element such as an adhesive; wherein the periphery of the sealing substrate is positioned inside the periphery of the substrate, and the peripheral portion of the electrode layer is connected to the wiring of the power source within the sealing portion.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 14, 2020
    Assignee: EL TECHNOLOGY FUSION GODO KAISHA
    Inventors: Hidekazu Kobayashi, Osamu Yokoyama, Yojiro Matsueda