Including Resistor Element Patents (Class 257/363)
-
Patent number: 7250660Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.Type: GrantFiled: July 14, 2004Date of Patent: July 31, 2007Assignee: Altera CorporationInventors: Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey Tyhach, Guu Lin, Chiakang Sung, Stephanie T. Tran
-
Patent number: 7215005Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.Type: GrantFiled: March 2, 2004Date of Patent: May 8, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Ta-Lee Yu
-
Patent number: 7208814Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.Type: GrantFiled: August 20, 2004Date of Patent: April 24, 2007Assignee: Infineon Technologies AGInventor: Stefan Pompl
-
Patent number: 7205612Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.Type: GrantFiled: November 1, 2004Date of Patent: April 17, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jun Cai, Keng Foo Lo
-
Patent number: 7202549Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.Type: GrantFiled: May 19, 2004Date of Patent: April 10, 2007Assignee: Ricoh Company, Ltd.Inventors: Yasunori Hashimoto, Kimihiko Yamashita
-
Patent number: 7202533Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.Type: GrantFiled: September 29, 2005Date of Patent: April 10, 2007Assignee: Texas Instruments IncorporatedInventors: Eric W. Beach, Vladimir F. Drobny, Derek W. Robinson
-
Patent number: 7196377Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.Type: GrantFiled: April 22, 2005Date of Patent: March 27, 2007Assignee: NEC Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata, Morihisa Hirata
-
Patent number: 7180141Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).Type: GrantFiled: December 3, 2004Date of Patent: February 20, 2007Assignee: Texas Instruments IncorporatedInventors: Jarrod Randall Eliason, Glen R. Fox, Richard A. Bailey
-
Patent number: 7176553Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).Type: GrantFiled: September 26, 2003Date of Patent: February 13, 2007Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Grossi, Roberto Bez, Giorgio Servalli
-
Patent number: 7169661Abstract: A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional masking. An n-well is firstly formed in a p-type silicon substrate. A nitride film is then deposited and patterned to form a patterned mask layer. The patterned mask layer serves as a mask. A p-field region is formed in the n-well to form a CMOS resistor. The CMOS resistor according to the present invention has a resistance of 10 k?–20 k? per square.Type: GrantFiled: April 12, 2004Date of Patent: January 30, 2007Assignee: System General Corp.Inventors: Chih-Feng Huang, Tuo-Hsin Chien
-
Patent number: 7154158Abstract: As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.Type: GrantFiled: October 15, 2004Date of Patent: December 26, 2006Assignee: NEC Electronics CorporationInventors: Kuniko Kikuta, Makoto Nakayama
-
Patent number: 7145204Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).Type: GrantFiled: April 15, 2005Date of Patent: December 5, 2006Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli, John E. Kunz, Jr.
-
Patent number: 7112852Abstract: The electrostatic protection device provided between an input/output terminal and an internal circuit of a semiconductor device according to the present invention has a first insulated gate field effect transistor (MOS transistor) and a second MOS transistor that are connected mutually in parallel between an input/output wiring connected to the input/output terminal and an electrode wiring of a prescribed potential, where the first MOS transistor and the second MOS transistor are MOS transistors of the same channel type, the second MOS transistor has s higher drive capability than the first MOS transistor, and the electrostatic protection device is formed such that it is started by the first MOS transistor.Type: GrantFiled: April 23, 2002Date of Patent: September 26, 2006Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
-
Patent number: 7098511Abstract: The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.Type: GrantFiled: October 27, 2004Date of Patent: August 29, 2006Assignee: National Chiao Tung UniversityInventors: Ming-Dou Ker, Kun-Hsien Lin
-
Patent number: 7087978Abstract: The accuracy of the width measurement of a semiconductor resistor is improved by modifying the gate mask of a standard MOS transistor fabrication process to form an opening between regions of polysilicon that are used as a mask when the substrate or well material is implanted to form the resistor.Type: GrantFiled: August 1, 2003Date of Patent: August 8, 2006Assignee: National Semiconductor CorporationInventor: Richard F. Taylor
-
Patent number: 7084478Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.Type: GrantFiled: October 16, 2002Date of Patent: August 1, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
-
Patent number: 7075123Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.Type: GrantFiled: October 19, 2004Date of Patent: July 11, 2006Assignee: Yamaha CorporationInventors: Nobuaki Tsuji, Masao Noro, Terumitsu Maeno, Seiji Hirade
-
Patent number: 7061029Abstract: A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.Type: GrantFiled: February 24, 2005Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Wen-Fang Lee, Wei-Lun Hsu, Yu-Hsien Lin
-
Patent number: 7045863Abstract: An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain silicide film is not provided in a portion located on a boundary of each transistor and divided to correspond to the respective transistors. As a result, regions between respective pairs of the transistors have high resistances, and it is, therefore, possible to prevent a current from flowing between the different transistors and prevent local current concentration. It is thereby possible to allow the electrostatic discharge protected transistor to make most use of an electrostatic destruction protection capability per unit area without increasing an area of the transistor.Type: GrantFiled: January 5, 2005Date of Patent: May 16, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiro Kogami, Katsuhiro Ootani, Katsuya Arai
-
Patent number: 7038297Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.Type: GrantFiled: January 21, 2004Date of Patent: May 2, 2006Assignee: Winbond Electronics CorporationInventors: Paul Vande Voorde, Chun-Mai Liu
-
Patent number: 7012307Abstract: An output buffer with a pull down circuit. The pull down circuit is coupled between a second power line and a pad, and has a resistor, a diode and an electrostatic discharge protection component. The resistor deposited on the substrate of a first conductivity type includes a well region of a second conductivity type. The resistor and the electrostatic discharge protection component are connected in series between the pad and the second power line. The diode is formed in the well region, construct by the PN junction formed between a first doped region of the first conductivity type and the well region. The first doped region is electrically floated in the well regions. During an electrostatic discharge event, the pad is instantaneously connected to the first doped region which will help to boost the turn-on of the electrostatic discharge circuit, and further enhance the electrostatic protection effect.Type: GrantFiled: February 8, 2001Date of Patent: March 14, 2006Assignee: Winbond Electronics Corp.Inventors: Shi-Tron Lin, Wei-Fan Chen
-
Patent number: 7002218Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.Type: GrantFiled: February 26, 2004Date of Patent: February 21, 2006Assignee: Microchip Technology IncorporatedInventor: Randy L. Yach
-
Patent number: 7002216Abstract: Disclosed are architectures and method for semiconductor ESD protection using grouped diodes, with the diode groups being electrically separated by substrate resistance. The mixed diode/resistor groups are arranged to be in an off state under normal operating conditions and to discharge ESD current between power lines. The disclosed architectures and method protects circuits using different power supplies and/or voltage inputs.Type: GrantFiled: June 8, 2004Date of Patent: February 21, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Shao-Chang Huang
-
Patent number: 7002217Abstract: The present invention relates to structures and methods that reduce ESD damage to electronic devices. In an embodiment, the structure is a parallel plate dissipative capacitor formed by sandwiching a dissipative dielectric layer between two conductive layers in series to the electronic device. The dissipative dielectric layer includes a nonconductive dielectric doped with a voltage dependent resistive material that defines a conductive threshold voltage. The structure functions as a voltage dependent resistor in response to an applied voltage such as an ESD surge voltage exceeding the defined conductive threshold voltage and dissipates the applied voltage into thermal energy before it can reach the electronic device and cause damage. The dissipative dielectric layer restores to a dielectric and the structure functions as a capacitor when the excess voltage is depleted that is drops below the defined conductive threshold voltage.Type: GrantFiled: June 12, 2004Date of Patent: February 21, 2006Assignee: Solectron CorporationInventor: Tommy D. Hollingsworth
-
Patent number: 7002235Abstract: A semiconductor device has a semiconductor support substrate, a buried insulation film disposed on the semiconductor support substrate, and a single-crystal silicon active layer disposed on the buried insulation film. The buried insulation film has portions which have been removed so that remaining portions of the buried insulating film form buried insulating film island regions. The single-crystal silicon active layer has portions which have been removed so that remaining portions of the single-crystal silicon active layer form single-crystal silicon active layer island regions defining single-crystal silicon resistors of a resistance circuit.Type: GrantFiled: March 24, 2003Date of Patent: February 21, 2006Assignee: Seiko Instruments Inc.Inventor: Hisashi Hasegawa
-
Patent number: 6982451Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.Type: GrantFiled: March 27, 2003Date of Patent: January 3, 2006Assignee: Xilinx, Inc.Inventors: Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart, Steven P. Young, Kevin T. Look, Jan L. de Jong
-
Patent number: 6967378Abstract: A semiconductor integrated circuit device has a MOS transistor M2 including a parasitic diode Dx2 for preventing a reverse current due to a parasitic diode Dx1 of a MOS transistor M1. The semiconductor integrated circuit device further has a voltage setting circuit 1 for turning the MOS transistor M2 off in a reversely biased state, and an anti-reverse-current element 2 for preventing a reverse current from flowing through the voltage setting circuit 1 in a reversely biased state. In normal operation, a direct-current voltage within the withstand voltage range of the MOS transistor M2 is fed to the gate thereof according to the voltage applied to the conductive terminal 6y of the MOS transistor M2.Type: GrantFiled: February 26, 2004Date of Patent: November 22, 2005Assignee: Rohm Co., Ltd.Inventors: Nobuhiro Nishikawa, Koichi Inoue
-
Patent number: 6963111Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.Type: GrantFiled: June 13, 2003Date of Patent: November 8, 2005Assignee: Texas Instruments IncorporatedInventors: Vijay K. Reddy, Gianluca Boselli, Ekanayake A. Amerasekera
-
Patent number: 6953971Abstract: A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A first resistor is connected in parallel with the first MOS transistor. A second MOS transistor is connected in series with the first MOS transistor. The second MOS transistor has a gate and a source connected together, and a body connected to the voltage reference. A second resistor is connected in parallel with the second MOS transistor. A first terminal is connected to the source of the first MOS transistor, and a second terminal is connected to the source of the second MOS transistor. The first terminal is accessible externally after the integrated circuit has been encapsulated.Type: GrantFiled: February 11, 2002Date of Patent: October 11, 2005Assignee: STMircoelectronics SAInventors: Sébastien Laville, Serge Pontarollo
-
Patent number: 6924532Abstract: The present invention provides a field-effect power transistor having a first semiconductor region (10) with first channels (20) having a large ratio of a channel width (w) to a channel length (l) for conducting through an electric current from a source terminal (17) to a drain terminal (11) in a manner dependent on a signal at a gate contact (10?) of the first semiconductor region (10); at least one second semiconductor region (12) with second channels (22) having a small ratio of the channel width (w) to the channel length (l) for conducting through an electric current from the source terminal (17) to the drain terminal (11) in a manner dependent on a signal at the gate contact (12?) of the second semiconductor region (12); and a drive terminal (16) for providing a drive signal at the gate contacts (10?; 12?), a first predetermined resistor (14) in each case being provided between the gate contact (12?) of the at least second semiconductor region (12) and the drive terminal (16); and an overvoltage protectiType: GrantFiled: October 8, 2003Date of Patent: August 2, 2005Assignee: Infineon Technologies AGInventors: Frank Pfirsch, Markus Zundel
-
Patent number: 6921931Abstract: A the present invention provides an electrostatic discharge protection element to be used in a semiconductor integrated circuit providing MOSFET, comprising a thyristor and a trigger diode for triggering the thyristor into an ON-state, wherein the trigger diode provides an n-type cathode high concentration impurity region, a p-type anode high concentration impurity region and a gate formed between the two high concentration impurity regions, the gate being composed of the same material as that of a gate of MOSFET forming the semiconductor integrated circuit, and the thyristor provided with a p-type high concentration impurity region that forms a cathode and an n-type high concentration impurity region that forms an anode, and the p-type high concentration impurity region provides in a p well and connected to a resistor and/or the n-type high concentration impurity region provided in an n well and connected to a resistor.Type: GrantFiled: June 11, 2003Date of Patent: July 26, 2005Assignee: Sharp Kabushiki KaishaInventors: Kenichi Higashi, Alberto O. Adan
-
Patent number: 6919602Abstract: A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.Type: GrantFiled: December 16, 2002Date of Patent: July 19, 2005Assignee: Winbond Electronics Corp.Inventors: Shi-Tron Lin, Wei-Fan Chen
-
Patent number: 6919588Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.Type: GrantFiled: August 27, 2003Date of Patent: July 19, 2005Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Andy Strachan, Peter J. Hopper, Philipp Lindorfer
-
Patent number: 6906386Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.Type: GrantFiled: April 24, 2003Date of Patent: June 14, 2005Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
-
Patent number: 6891230Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.Type: GrantFiled: March 2, 2004Date of Patent: May 10, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ta-Lee Yu
-
Patent number: 6888201Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.Type: GrantFiled: March 2, 2004Date of Patent: May 3, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ta-Lee Yu
-
Patent number: 6882011Abstract: An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily doped region at the other side of the first gate. A second MOS transistor is laterally disposed in proximity to the first MOS transistor. The second MOS transistor includes a second gate, a third heavily doped region at one side of the second gate, and a fourth heavily doped region at the other side of the second gate. The floating gate MOS transistor is located between the first and second MOS transistors. A floating gate MOS transistor is serially connected to the first MOS transistor via the second heavily doped region and is serially connected to the second MOS transistor via the third heavily doped region.Type: GrantFiled: March 8, 2004Date of Patent: April 19, 2005Assignee: United Microelectronics Corp.Inventor: Shiao-Shien Chen
-
Patent number: 6879004Abstract: A spark gap device for protecting an integrated circuit. The spark gap device includes a first node for receiving an input signal and a second node to be protected. A first conductive layer is conductively interfaced to the first node and the second node and disposed therebetween. A second conductive layer is connected to a sink voltage and separated from the first conductive layer by an insulating layer of a predetermined thickness. A portion of the first conductive layer is disposed proximate to the second conductive layer and not overlying the second conductive layer, such that a gap is formed therebetween and the gap having a dimension that is greater than the thickness of the insulating layer.Type: GrantFiled: November 5, 2002Date of Patent: April 12, 2005Assignee: Silicon Labs CP, Inc.Inventors: Ka Y. Leung, Douglas R. Holberg
-
Patent number: 6873028Abstract: A chip resistor comprising a substrate having opposite parallel symmetrical first and second surfaces, a central longitudinal plane of symmetry, separate and spaced first and second resistive layers on the first and second surfaces. The resistive layers are electrically connected in parallel to each other and the first and second surfaces of the substrate are symmetrically located with respect to and equidistant from a central longitudinal plane. Thus, when electrical current passes through the resistive layers, a temperature distribution within the substrate will be substantially symmetrical about the central longitudinal plane of the substrate for eliminating thermal bending thereof. The splitting of the surge current between two resistive layers results in the lower temperature in each resistive layer when compared with the temperature in the single resistive layer of the prior art chip resistor loaded by the same current.Type: GrantFiled: November 15, 2001Date of Patent: March 29, 2005Assignee: Vishay Intertechnology, Inc.Inventor: Michael Belman
-
Patent number: 6873016Abstract: A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.Type: GrantFiled: October 3, 2003Date of Patent: March 29, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Taek Park, Hong-Soo Kim
-
Patent number: 6867461Abstract: The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.Type: GrantFiled: April 1, 2004Date of Patent: March 15, 2005Assignee: National Chiao Tung UniversityInventors: Ming-Dou Ker, Kun-Hsien Lin
-
Patent number: 6864536Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.Type: GrantFiled: December 20, 2000Date of Patent: March 8, 2005Assignee: Winbond Electronics CorporationInventors: Shi-Tron Lin, Wei-Fan Chen, Chenhsin Lien, Wan-Yun Lin
-
Patent number: 6858900Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.Type: GrantFiled: October 8, 2001Date of Patent: February 22, 2005Assignee: Winbond Electronics CorpInventors: Wei-Fan Chen, Shi-Tron Lin, Chuan-Jane Chao
-
Patent number: 6853036Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention focus on preventing ESD protection circuit failure due to elastic waves within the materials of an integrated circuit. The elastic waves are specifically caused by very fast ESD discharge events. Disclosed are ESD protection circuits incorporating materials with superior thermo-mechanical properties, in particular, material damping, melting temperature, material stiffness, elastic modulus, tensile strength and fracture toughness. Also disclosed is the use of thermo-mechanical energy absorber material that is designed to protect ESD devices from failure due to slower ESD events.Type: GrantFiled: August 6, 2003Date of Patent: February 8, 2005Assignee: ESD Pulse, Inc.Inventors: Vladimir Rodov, Wlodzimierz Woytek Tworzydlo
-
Patent number: 6847059Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.Type: GrantFiled: October 18, 2001Date of Patent: January 25, 2005Assignee: Yamaha CorporationInventors: Nobuaki Tsuji, Masao Noro, Terumitsu Maeno, Seiji Hirade
-
Patent number: 6844573Abstract: In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.Type: GrantFiled: August 28, 2002Date of Patent: January 18, 2005Assignee: Advanced Micro Devices, IncInventor: Richard C. Blish, II
-
Patent number: 6838747Abstract: A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a resistive element (6). The density of crystal defects in the second regions (52, 62) is higher than that in first regions (51, 61). The density of crystal defects in a polycrystalline silicon film (70) for a resistive element (7) is higher near a silicide film (73). A polycrystalline silicon film (80) for a resistive element (8) is in contact with a substrate (2) with a silicide film in an opening of an isolation insulating film (3). The density of crystal defects in a substrate surface (2S) near the silicide film is higher than that in the vicinity. With such a structure, a current leak in an isolation region can be reduced.Type: GrantFiled: July 11, 2002Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventor: Hidekazu Oda
-
Patent number: 6838323Abstract: A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.Type: GrantFiled: January 13, 2003Date of Patent: January 4, 2005Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Edward J. Nowak, Xiaowei Tian, Minh H. Tong, Steven H. Voldman
-
Patent number: 6833590Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.Type: GrantFiled: March 4, 2003Date of Patent: December 21, 2004Assignee: Renesas Technology Corp.Inventors: Chikao Makita, Kunihiko Karasawa
-
Patent number: 6825517Abstract: Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.Type: GrantFiled: August 28, 2002Date of Patent: November 30, 2004Assignee: COVA Technologies, Inc.Inventors: Klaus Dimmler, Alfred P. Gnadinger