Abstract: A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

Abstract: A power supply terminal is supplied with a power supply potential. A reference terminal is supplied with a reference potential. First and second p-channel MOS transistor, and first and second n-channel MOS transistor each has a gate, a source, a drain, and a back gate. The gate, source and back gate of the first pMOS transistor, the back gate of the second pMOS transistor, and the gate and drain of the second nMOS transistor are connected to the power supply terminal. The source of the second pMOS transistor is connected to the drain of the first pMOS transistor. The gate and drain of the second pMOS transistor, the gate, source and back gate of the first nMOS transistor, and the back gate of the second nMOS transistor are connected to the reference terminal. The source of the second nMOS transistor is connected to the drain of the first nMOS transistor.

Abstract: A semiconductor device having an input circuit for effectively preventing breakdown caused by an electrostatic surge is provided. A first NMOS transistor is connected between an input terminal and an internal node, and a gate electrode of the first NMOS transistor is connected to a power supply line via a PMOS transistor that is always in an ON state. Therefore, the first NMOS transistor is also always in the ON state. Further, a second NMOS transistor, which is always in an OFF state, is connected between the internal node and a ground line. Even when an electrostatic surge voltage is applied to the input terminal, the electrostatic surge voltage is not directly applied to the gate electrode of the first NMOS transistor. Thus, breakdown of a gate oxide film of the gate is prevented.

Abstract: A microwave-frequency microcircuit assembly includes an integrated circuit structure having a circuit ground. A support structure includes a grounded metallic carrier, and a dielectric substrate having a top surface, a bottom surface contacting the carrier, and a capacitor via extending through the dielectric substrate. A metallization on the top surface of the substrate includes an input metallization trace to the integrated circuit structure, an output metallization trace from the integrated circuit structure, and a substrate ground plane upon which the integrated circuit structure is affixed. A thin-film capacitor resides in the capacitor via and is electrically connected between the substrate ground plane and the carrier. An electrical resistor is connected between the circuit ground of the integrated circuit structure and the carrier to self-bias the integrated circuit structure.

Abstract: A semiconductor device include a current source having a first node coupled to a first voltage reference node, and a second node for extracting a current in response to an electrostatic discharge (ESD) on a terminal. The device further includes a transistor having a well and a control electrode, a first current electrode coupled to a second voltage reference node, and a second current electrode coupled to the second node of the current source, and includes a resistive element is coupled to the terminal and the second node of the current source. The transistor of the semiconductor device is biased by detecting a positive voltage event (such as an ESD) at the first current electrode of the transistor, and biasing the first current electrode of the transistor in response to detecting the positive voltage event, wherein the biasing of the first current electrode is for preventing a forward biasing of an n-p junction associated with the transistor.

Abstract: The present invention includes integrated circuitry, an interface circuit of an integrated circuit device, cascode circuitry, method of protecting an integrated circuit, method of operating integrated circuitry, and method of operating cascode circuitry. One aspect of the present invention provides integrated circuitry including a driver adapted to couple with a pad and internal circuitry of an integrated circuit device, the driver includes a first transistor coupled with the pad; cascode circuitry including a second transistor coupled with the pad and a third transistor coupled with ground, the cascode circuitry configured to remain in an untriggered state during the presence of stress currents at the pad; and protection circuitry intermediate the pad and ground and configured to shunt stress currents from the pad to ground.

Abstract: A tunable high voltage trigger silicon controlled rectifier (SCR) with a high holding voltage is disclosed. The source of a drain extended MOS serves as the remote cathode for the SCR, while the drain of the drain extended MOS serves to generate avalanche currents to trigger the SCR.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.

Abstract: The present invention provides an ESD protection circuit having at least one semiconductor-controlled rectifier and a diode. The SCR having a floating anode gate is connected between a first circuit node a second circuit node. The diode is connected between an anode and a cathode gate of the SCR to activate the SCR so that a potential between the first circuit node and second circuit node can be clamped at about a holding voltage of the SCR during an ESD event.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: An electrostatic discharge (ESD) protective structure is configured to protect an integrated circuit, which is connected between a first voltage bus with a first supply voltage and a second voltage bus with a second supply voltage. The ESD protective structure includes a plurality of laterally designed bipolar transistors, whose load lines are arranged parallel to one another and between the voltage buses, and whose control connections are connected to one of the voltage buses. A resistor track is disposed in the load line of each bipolar transistor and is co-integrated into the ESD protective structure on the collector side and/or the emitter side.

Abstract: An improved light responsive semiconductor switch with shorted load protection capable of successfully interrupting a load overcurrent. The switch is includes an output transistor which is triggered by a photovoltaic element to connect a load to a power source thereof, and an overcurrent sensor which provides an overcurrent signal upon seeing an overcurrent condition in the load. A shunt transistor is connected in series with a current limiting resistive element across the photovoltaic element to define a shunt path of flowing the current from the photovoltaic element through the current limiting resistive element away from the output transistor. A latch circuit is included to be energized by the photovoltaic element and to provide an interruption signal once the overcurrent signal is received and hold the interruption signal.

Abstract: A ballasting resistor incorporating therein an H-shaped gate structure reduces a current therethrough by utilizing a pinching effect. The ballasting resistor is formed on a silicon-on-insulator substrate and includes a pair of N+ regions, a P− body region formed between the NM regions, and a pair of P+ nodes connected to the P− body region. The P− body region resides under the gate structure, which includes a thin dielectric layer formed on the P− body region and a conductive layer formed on the dielectric layer. The ballasting resistor is biased in such a manner that the P-N junctions are reverse-biased to pinch down the cross-sectional area of the current path provided inside the P− body region between the nodes as an applied voltage increases. The ballasting resistor has a MOS transistor-like structure; and, therefore, electrostatic discharge protection can be provided for the conventional SOI MOS circuits without requiring additional processing steps.

Abstract: A protective circuit includes a pair of diodes to protect the gate dielectric of an insulated-gate semiconductor device from over-voltage conditions, such as can occur during plasma etch manufacturing processes. The diodes are either anode- or cathode-coupled, and are connected between the gate of the device and bulk ground. Because of their opposing polarities, one of the diodes is always reverse-biased regardless of whether a positive or negative control voltage is applied to the gate of the device. As a result, the protective circuit imposes no operational restrictions on normal control voltages. At the same time, the circuit limits any plasma-induced charge buildup that can arise during manufacturing. If the gate voltage rises, a first of the two diodes is reverse biased and prevents the protective circuit from conducting. When the gate voltage reaches the reverse breakdown voltage of the first diode (plus the small forward voltage drop of the second diode), both diodes begin to conduct.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.

Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.

Abstract: A MOS transistor structure is provided for ESD protection in an integrated circuit device. A trench controls salicide deposition to prevent hot spot formation and allows control of the turn-on voltage. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusions on either side of the gate. A drain trench is located to separate the salicide between a drain contact and the gate edge, and by controlling the size and location of the drain trench, the turn-on voltages can be controlled; i.e., the turn-on voltage due to drain diffusion region to substrate avalanche breakdown and the turn-on voltage due to source well to drain well punch-through. Thus, very low turn-on voltages may be achieved for ESD protection.

Abstract: An ink jet printhead having a ground bus that partially overlies active regions of FET drive circuits.

Abstract: A protective circuit in a semiconductor device includes a protective n-channel MOS transistor connected between the power source line and the ground line, with the gate and drain being connected together, and an n-p-n transistor having a base connected to the source of the protective n-channel MOS transistor and connected between the power source line and the ground line. The protective circuit disposed in a low-voltage semiconductor device has a lower power dissipation due to a low junction leakage current.

Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the fill width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.

Abstract: The invention relates to an edge structure and a drift region for a semiconductor component. A semiconductor body of the one conductivity type has an edge area with a plurality of regions of the other conductivity type embedded in at least two mutually different planes. Underneath an active zone of the semiconductor component the regions are connected over different planes via connection zone, but the regions are otherwise floating.

Abstract: The present invention discloses an ESD damage immunity buffer, comprising: a gate, a first doped region, a second doped region, a third doped region, and a resist layer. The ESD damage immunity buffer, which is in parallel with an ESD protection circuit, is connected to a pad and the circuit grounding node. The gate is formed on the semiconductor substrate, and the first doped region and the second doped region are formed adjacent to the region below the gate in the semiconductor substrate and electrically coupled to the ground. The third doped region is formed in the semiconductor substrate and electrically coupled to the pad. Further, a resist layer is formed upon the semiconductor substrate and connects the third doped region to the second doped region, wherein said resist layer ensures a triggering of the ESD protection circuit prior to the ESD damage immunity buffer during an ESD event.

Abstract: A resistor comprising a substrate typically made of aluminum, a pair of top electrode layers made of a thin noble metal film disposed on both ends of the top face of the substrate, and a resistance layer of a thin metal film made of Ni system or Cr system disposed on the top face of the substrate so as to electrically connect with the top electrode layer. The moisture absorbency of a protective layer is reduced to upgrade sealing of the resistance layer by covering the resistance layer with two resin layers: a first protective layer made of polyimide resin and a second protective layer made of epoxy resin, which have different water vapor permeability, to improve the reliability, particularly the moisture resistance characteristics, of the resistor.

Abstract: An integrated semiconductor circuit has a protection structure for protecting against electrostatic discharge. The protection element has at least one integrated vertical protection transistor, whose load path is connected between the terminal pad and a potential rail. The base of the vertical npn bipolar transistor is controlled by a diode at breakdown, whose breakdown voltage is above the holding voltage of the npn bipolar transistors. By suitably choosing the location of the base contact, of the pn junction of the breakdown diode, and of the emitter, a desired adjustment of the trigger current is possible. Thus a variation in the voltage drop at the base is achieved which enables a current flow. The signal voltage requirements can be met and at the same time, an optimization of the ESD strength is achieved. The control or trigger sensitivity of the base can also be adjusted by means of an integrated resistor, which is disposed in the base zone.

Abstract: A semiconductor device includes a transistor and a protective resistance element. The transistor has first and second impurity regions of a first conductivity type formed on a surface of a substrate and serving as a source and a drain, respectively, and a gate electrode formed on a channel region sandwiched between the first and second impurity regions through a gate insulating film. The protective resistance element has a third impurity region of the first conductivity type formed on the surface of the substrate to be separated from the second impurity region by a predetermined distance, a control electrode formed on the substrate through an insulating film in a surface region sandwiched between the second and third impurity regions, and a well of the first conductivity type formed on the surface of the substrate in the surface region sandwiched between the second and third impurity regions to come into contact with them.

Abstract: The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.

Abstract: An SCR provides for increased holding voltage by decoupling the pnp and npn parasitic bipolar transistors of the SCR. In one embodiment, a N+ region is placed between the n+ region and the p+ region normally associated with conventional SCR devices, to formulate a new resistance. The new resistance is manifested to allow more current to flow through the new resistance rather than through the SCR parasitic pnp bipolar transistor. Since the parasitic pnp bipolar transistor no longer turns on as strongly as it would otherwise without the low resistance path through the new resistor, the holding voltage of the SCR is raised.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a source region of a second conductivity type, a drain region of the second conductivity type, and a first insulating layer formed over the major surface between the source region and the drain region. The device also includes a control electrode layer formed over the first insulating layer and a second insulating layer formed over the major surface. The device also includes a first wiring layer formed in the first contact hole and a second wiring layer formed in the second contact hole and connected to a pad and an internal circuitry, wherein the internal circuitry executes a predetermined operation and wherein the pad receives a signal from the internal circuitry or a signal from an external device.

Abstract: Electrostatic breakdown is avoided during fabrication of individual semiconductor devices using a semiconductor aggregate substrate. The semiconductor aggregate substrate is comprised of a large wafer. A plurality of sections are provided on the surface of the wafer, which are divided by division lines. A display active matrix circuit is integrally formed in each of the segments through normal IC production processing. Guard ring patterns are provided so that they surround the individual display active matrix circuits. A connection pattern is also provided for commonly connecting the guard ring patterns adjoining each other through the division lines. The connection pattern has opening structures for dealing with an external overcurrent on both sides of the division lines. The opening structures are constituted by, for example fuse patterns.

Abstract: A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.

Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: In a semiconductor device, in order to protect an interior of the device, protective circuits are provided. The protective circuits include a first circuit connected between the first terminal and a negative potential line, a second circuit connected between the first terminal and a ground potential line, and a third circuit connected between the ground potential line and a second terminal. The first circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the negative potential line, and a gate connected with the first terminal or the negative potential line. The second circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the ground potential line, and a gate connected with the first terminal or the ground potential line.

Abstract: An ESD protection circuit for dual 3V/5V supply devices. ESD protection circuit 10 comprises a switching element 12 connected between a bond pad 14 and primary protection device 16. Primary protection device 16 comprises MOS circuitry designed for 3V operation that suffers from oxide reliability problems when 5V signals are applied directly. Switching element 12 separates the primary protection device 16 from 5V signals which may appear at bond pad 14.

Abstract: In order to protect an internal circuit from high voltages caused by static electricity applied to a pad of a semiconductor device, a protection circuit is configured of a clamping circuit portion (6) utilizing a MISFET (5) connected between the pad (10) and the internal circuit (3) and a gate circuit portion (8) connected to the clamping circuit portion (6). The source and bulk terminals of the MISFET (5) of the clamping circuit portion (6) are connected to the pad (10) and the internal circuit (3), the drain thereof is connected to a first power supply terminal (11), the gate thereof is connected to one terminal of a gate circuit resistor (15) and one terminal of a capacitor (16) constituting the gate circuit portion (8), the other terminal of the gate circuit resistor (15) is connected to a second power supply terminal (12), and the other terminal of the capacitor (16) is connected to the first power supply terminal (11).

Abstract: A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor region

Abstract: A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor.

Abstract: A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Abstract: A semiconductor device provided with a planar bipolar transistor and a built-in ingredient acting as an element to protect the bipolar transistor from an external surge voltage e.g. an electrostatic surge voltage and the like, is provided with a planar bipolar transistor further provided with a doped region having a conductivity opposite to that of a semiconductor substrate in which the foregoing planar bipolar transistor is produced, the doped region being produced along the top surface of the semiconductor substrate at a location close to the bipolar transistor, and the emitter of the bipolar transistor being connected the doped region and a fixed potential (V.sub.EE) or the ground potential, whereby the operation speed of a circuit including the transistor is not reduced by potential parasitic capacitors which otherwise accompany the built-in ingredients produced to protect the transistor from an external surge voltage e.g. an electrostatic surge voltage and the like.

Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

Abstract: The present invention relates to an apparatus and method for protecting a semiconductor device, and more particularly to an n-type metal-oxide semiconductor (NMOS) transistor with a ladder structure, used for protecting a semiconductor device from electrostatic discharge. In the present invention, a plurality of drain branches are connected by resistors, and a contact point of the well and the source/well pattern is formed only alongside the drain branch of the ladder structure which is nearest an input/output terminal of the semiconductor device. Accordingly, the current is better dispersed to all of the drain branches, thereby preventing the voltage breakdown of the transistor due to heat caused by the localization of current in the drain branch farthest from the input/output terminal.

Abstract: An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.

Abstract: A polysilicon resistor is added between a source (ground or power) of an EMI core circuitry and a source of the EMI peripheral circuitry. In this way, the electromagnetic interference of an integrated circuit is reduced. The added polysilicon resistor reduces the di/dt of the current passing between the power and the ground of the EMI core circuitry so that the EMI is reduced.

Abstract: The device has an SCR structure in a P surface zone of a silicon die. A P+ anode region for connection to an I/O terminal to be protected is formed in an N region, as well as an N+ contact region; an N+ cathode region is formed in another N region for connection to the earth of the integrated circuit. The striking potential of the SCR, that is, the intervention potential of the protection device, is determined by the reverse breakdown of the junction between the first N region and the P-body surface zone. This potential is influenced by an electrode which is disposed over the junction and is connected to the cathode constituting the gate of a cut-off N-channel MOS transistor. The concentrations are selected in a manner such that the P-channel MOS transistor defined by the P region, by the portion of the first region over which the electrode is disposed, and by the P-body, has a conduction threshold greater than the striking potential.

Abstract: According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: According to the present invention, a MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate comprises a high melting point metal silicide layer disposed on the drain diffusion layer through a first insulating film, a metal wire layer disposed on the high melting point metal silicide layer through a second insulating film, at least two first contact holes for electrically connecting the high melting point metal silicide layer and the metal wire layer, and a second contact hole for electrically connecting the high melting point metal silicide layer and the drain diffusion layer, wherein the second contact hole is disposed at a substantial center between the two first contact holes.

Abstract: An input protective circuit includes a resistance element for connecting the input terminal and internal circuit of a semiconductor integrated circuit, and a field effect transistor for discharging a surge input to the ground potential. Adjacent diffusion layer regions consisting of a diffusion resistance layer corresponding to the resistance element and an impurity diffusion layer corresponding to the drain or source of the field effect transistor and connected adjacent to each other are formed by double diffusion using ion implantation.

Abstract: The present invention provides an electrostatic breakdown protecting device which has a high electrostatic breakdown resistance, a high latch up resistance and an excellent protective ability and which has no dead space in the vicinity of protective elements. The present invention includes an I/O terminal directly connected to a protective diode comprising a p-type diffusion layer 103a and an n-type diffusion layer 102b, and an NPN protective bipolar transistor comprising n-type diffusion layers 102b, 102c and a p-type well 113 and connected to an NMOSFET for protection comprising n-type diffusion layers 102c, 102d and a gate electrode 105 via an input resistor 114. These protective elements are formed on the p-type well 113 separated from a substrate for an internal circuit by an n-type buried diffusion layer 111 and an n-type well 112. The internal circuit to be protected is connected to a drain 102d of the NMOSFET for protection.

Abstract: A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.