Combined With Bipolar Transistor Patents (Class 257/370)
  • Patent number: 10580877
    Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 3, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 10573713
    Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 25, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Wen-Ying Wen, MD Imran Siddiqui, Yu-Chi Chang
  • Patent number: 10566423
    Abstract: A semiconductor switch device for switching an RF signal and a method of making the same. The device includes a first semiconductor region having a first conductivity type. The device also includes a source region and a drain region located in the first semiconductor region. The source region and the drain region have a second conductivity type. The second conductivity type is different to the first conductivity type. The device further includes a gate separating the source region from the drain region. The device also includes at least one sinker region having the second conductivity type. Each sinker region is connectable to an external potential for drawing minority carriers away from the source and drain regions to reduce a leakage current at junctions between the source and drain regions and the first semiconductor region.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: February 18, 2020
    Assignee: NXP B.V..
    Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Anurag Vohra, Jan Willem Slotboom
  • Patent number: 10546852
    Abstract: A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ranadeep Dutta, Matthew Michael Nowak
  • Patent number: 10431581
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region disposed adjacent to the substrate, a first fin disposed above the well region, a second fin disposed above the substrate, and a gate region disposed adjacent to each of the first fin and the second fin. The semiconductor device may also include at least one third fin disposed above the substrate, a support layer disposed above the at least one third fin, and a compound semiconductor device disposed above the support layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Gengming Tao, Bin Yang
  • Patent number: 10424579
    Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 24, 2019
    Assignee: IMEC vzw
    Inventors: Mirko Scholz, Shih-Hung Chen
  • Patent number: 10347737
    Abstract: Methods for manufacturing a bipolar junction transistor are provided. A method includes providing a semiconductor substrate having a trench isolation, where a pad resulting from a manufacturing of the trench isolation is arranged on the semiconductor substrate, providing an isolation layer on the semiconductor substrate and the pad such that the pad is covered by the isolation layer, removing the isolation layer up to the pad, and selectively removing the pad to obtain an emitter window.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Claus Dahl, Dmitri Alex Tschumakow
  • Patent number: 10325907
    Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 18, 2019
    Assignee: Newport Fab, LLC dba Jazz Semiconductor, Inc.
    Inventors: Kurt A. Moen, Edward J. Preisler, Paul D. Hurwitz
  • Patent number: 10312159
    Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventors: Frank Hoffmann, Dirk Manger, Andreas Pribil, Marc Probst, Stefan Tegen
  • Patent number: 10290631
    Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Newport Fab, LLC
    Inventors: Kurt A. Moen, Edward J. Preisler, Paul D. Hurwitz
  • Patent number: 10283584
    Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, Andrei Sidelnicov, El Mehdi Bazizi
  • Patent number: 10232043
    Abstract: Disclosed herein are methods and compositions for the modulation of the activity of electrically excitable cells. In particular, several embodiments relate to the use of photovoltaic compounds which, upon exposure to light energy, increase or decrease the electrical activity of cells.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: March 19, 2019
    Assignees: California Institute of Technology, University of Southern California
    Inventors: Melanie A. Yen, Dennis A. Dougherty, Robert H. Grubbs, Harry B. Gray, Robert H. Chow, Mark S. Humayun, Mark E. Thompson, Lionel E. Cheruzel
  • Patent number: 10192864
    Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning
  • Patent number: 10163728
    Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu
  • Patent number: 10163892
    Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michel J. Abou-Khalil, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 10134637
    Abstract: A semiconductor component is formed by providing a substrate having partially formed first and second transistors, a base electrode stack formed over the transistors, first and second emitter windows formed in the electrode stack over first and second collector regions of the transistors, and an oxide layer extending over the collector regions. A process entails forming a mask layer in a selected emitter window, optionally forming a selectively implanted collector (SIC) in an un-masked emitter window, and removing an oxide layer and forming an epitaxial layer in the un-masked emitter window. The process further entails forming an oxide layer over the epitaxial layer and repeating the operations of forming a mask layer for another selected emitter window, optionally forming a SIC in another un-masked emitter window, and removing an oxide layer and forming an epitaxial layer in the un-masked emitter window. The epitaxial layers may have different epitaxial growth profiles.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 20, 2018
    Assignee: NXP USA, Inc.
    Inventor: Jay Paul John
  • Patent number: 10115788
    Abstract: A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm2 to about 1E19 atoms/cm2, and a barrier layer formed above the APT layer. A method of forming a semiconductor device having a horizontal gate all around structure is also provided.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 10109740
    Abstract: An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers. Two conductive regions are disposed adjacent to the gate structure and on opposite sides of the gate structure. A dielectric barrier is formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10090340
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10090200
    Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 2, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Yanjie Lian, Daping Fu, Ji-Hyoung Yoo
  • Patent number: 10079278
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 10074649
    Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Monfray, Gaspard Hiblot
  • Patent number: 10074716
    Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: September 11, 2018
    Assignees: SKYWORKS SOLUTIONS (HONG KONG) LIMITED, ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
    Inventors: Wai Tien Chan, Donald Ray Disney, Richard K. Williams
  • Patent number: 10062774
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a semiconductor layer; a gate electrode filled via a gate insulating film in the plurality of gate trenches; an n+-type emitter region, a p-type base region, and an n?-type drift region disposed laterally to each gate trench; a p+-type collector region on a back surface side of the semiconductor layer; a plurality of emitter trenches formed between the gate trenches adjacent to each other; a buried electrode filled via an insulating film in the plurality of emitter trenches; and a p-type floating region formed between the plurality of emitter trenches. The p-type floating region is formed deeper than the p-type base region, and includes an overlap portion. The n+-type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10043872
    Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 7, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9984196
    Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih Ming Yang, Yi-Kan Cheng
  • Patent number: 9972244
    Abstract: A display device includes: a plurality of light-emitting elements, each light-emitting element having a light-emitting unit and a driving circuit for driving the light-emitting unit. The driving circuit at least includes (A) a drive transistor having source/drain regions, a channel forming region, and a gate electrode, (B) a video signal write transistor having source/drain regions, a channel forming region, and a gate electrode, and (C) a capacitive unit. In the drive transistor, (A-1) one of the source/drain regions is connected to the corresponding current supply line, (A-2) the other region of the source/drain regions is connected to the light-emitting unit and connected to one end of the capacitive unit, and forms a second node, and (A-3) the gate electrode is connected to the other region of the source/drain regions of the video signal write transistor and connected to the other end of the capacitive unit, and forms a first node.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Sony Corporation
    Inventors: Junichi Yamashita, Yusuke Onoyama, Tetsuo Minami, Naobumi Toyomura, Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9922980
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming a diamond film on the substrate, etching the diamond film to form a first trench that extends to the substrate, epitaxially growing a first semiconductor material in the first trench to form a first semiconductor fin structure, and removing an upper portion of the diamond film to expose an upper portion of the first semiconductor fin structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 20, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 9899437
    Abstract: A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 20, 2018
    Assignee: INTELLECTUAL VENTURES II LLC
    Inventor: Won-Ho Lee
  • Patent number: 9865792
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Patent number: 9824965
    Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: November 21, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Qian Tao, Boon Keat Tan, Richard Lum Kok Keong
  • Patent number: 9793372
    Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 9793182
    Abstract: A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventor: Francisco Javier Santos Rodriguez
  • Patent number: 9793256
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 9773784
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 26, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 9773734
    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Gurtej S. Sandhu
  • Patent number: 9768282
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×1016 cm?3. According to certain embodiments, the collector includes two gradings. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 19, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Peter J. Zampardi, Jr.
  • Patent number: 9712165
    Abstract: A semiconductor device includes: a first power source (PS1) pad supplied with a PS1 voltage; a PS1 line connected to the PS1 pad; a first ground line (G1); an output circuit operated using the PS1 voltage; a second power source (PS2) pad supplied with a PS2 voltage; a PS2 line connected to the PS2 pad; a second ground line (G2); a signal line connected to an output end of the output circuit; an input circuit connected to the signal line at an input end receiving a signal from the output end and operated using the PS2 voltage; a main protection circuit unit providing discharge routes between the PS1 pad and G1, G1 and G2, and G2 and the PS2 pad; and a sub protection circuit unit. The output circuit includes: a circuit element arranged between the PS1 line and the signal line and able to function as a resistive element.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Mototsugu Okushima
  • Patent number: 9698044
    Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Ruey-Hsin Liu, Hsiao-Chin Tuan
  • Patent number: 9691865
    Abstract: A high frequency semiconductor device includes a stacked body, a gate electrode, a source electrode and a drain electrode. The gate electrode includes a bending gate part and a straight gate part. The bending gate part is extended in a zigzag shape and has first and second outer edges. The source electrode includes a bending source part and a straight source part. The bending source part has an outer edge spaced by a first distance from the first outer edge of the bending gate part along a normal direction. The drain electrode includes a bending drain part and a straight drain part. The bending drain part has an outer edge spaced by a second distance from the second outer edge of the bending gate part along the normal direction.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaishi Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9679963
    Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 13, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
  • Patent number: 9634129
    Abstract: An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 25, 2017
    Assignee: SEMICONDUCTOR COMPONENT INDUSTRIES, LLC
    Inventor: Takumi Hosoya
  • Patent number: 9627521
    Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 18, 2017
    Assignee: IXYS Corporation
    Inventor: Vladimir Tsukanov
  • Patent number: 9595948
    Abstract: A semiconductor device has a drive unit outputting a first drive signal to a first electrode and a second drive signal to a second electrode, an instruction signal generation unit generating an instruction signal as a basis of the drive signals and a control unit outputting a first control signal as a basis of the first drive signal and a second control signal as a basis of the second drive signal, based on the instruction signal to control the drive unit. The control unit synchronizes the first control signal with the instruction signal, delays a turning-on timing of the second control signal by a predetermined time relative to the instruction signal and determines a turning-off timing of the second control signal based on a previous pulse width of the instruction signal.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: March 14, 2017
    Assignee: DENSO CORPORATION
    Inventor: Hironori Akiyama
  • Patent number: 9595500
    Abstract: A semiconductor device includes: a semiconductor chip having a switching element and multiple pads electrically connected to the switching element; and multiple lead terminals electrically connected to the respective pads. The multiple lead terminals include a control terminal used for control of on/off operation of the switching element, and a main terminal into which a main current flows when the switching element is in an on state. A coupling coefficient k falls within a range of ?3%?k?2%, where the coupling coefficient k is defined by a parasitic inductance Lg in a current path of a control current flowing in the control terminal, a parasitic inductance Lo in a current path of the main current, and a mutual inductance Ms of the parasitic inductances Lg and Lo.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 14, 2017
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Patent number: 9548421
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9548298
    Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTUMENTS INCORPORATED
    Inventors: Weidong Tian, YuGuo Wang, Tathagata Chatterjee, Rajni J. Aggarwal
  • Patent number: 9543403
    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Qizhi Liu
  • Patent number: 9531466
    Abstract: A diversity reception circuit obtains a synthesized output based on signals received at a plurality of antennas. The diversity reception circuit includes a plurality of PLLs outputting respective local oscillation signals; a plurality of mixers converting respective received radio frequency signals to low frequency signals; and a switch circuit selecting any one of outputs of the PLLs and supplying the selected output to at least one of the mixers.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 27, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Atsushi Ohara, Yoshifumi Hosokawa, Yoshihiro Okumura
  • Patent number: 9530693
    Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jong Il Kim