Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.

Abstract: This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.

Abstract: A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Abstract: An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper surface of the n-type base layer; an n-type source layer provided in part of an upper surface of the p-type base layer; a trench extending through the n-type source layer and the p-type base layer to the n-type base layer; a gate electrode provided in the trench; and a gate insulating film provided between the gate electrode and an inner surface of the trench. The p-type emitter layer has a thickness of 5 to 50 ?m and a dopant concentration of 2×1016 to 1×1018 cm?3.

Abstract: The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N? layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N? layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N? layer in an area contained in the body layer in plane view.

Abstract: Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.

Abstract: This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal.

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Abstract: A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a collector, a base and an emitter. The emitter of the bipolar transistor is formed to serve as the source region for the MOS transistor and the base of the bipolar transistor is formed to serve as a capacitive charge storage region for the memory cell.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.

Abstract: A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.

Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

Abstract: A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming sour

Abstract: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

Abstract: A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

Abstract: A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.

Abstract: A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.

Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.

Abstract: The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.

Abstract: A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depth

Abstract: An ambipolar transistor, including a p-type semiconductor region and an n-type semiconductor region near the p-type semiconductor region. Also a first terminal and second terminal contact both the p-type semiconductor region and the n-type semiconductor region. Furthermore, the p-type semiconductor region and the n-type semiconductor region substantially do not overlap each other. A method of manufacturing an ambipolar transistor is also disclosed, including forming a p-type semiconductor region, forming an n-type semiconductor region near the p-type semiconductor region, forming a first terminal contacting both the p-type semiconductor region and n-type semiconductor region, forming a second terminal contacting both the p-type semiconductor region and n-type semiconductor region; and wherein the p-type semiconductor region and the n-type semiconductor region substantially do not overlap, and have substantially no interfacial area.

Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Abstract: A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: The present invention provides several embodiments with layout patterns for ESD protection. An apparatus with a layout pattern may be configured to protect I/O pads or the power rail. The layout pattern may designed to increase the current paths for ESD stress currents. For example, more rings may be applied. The present invention also provides circuit embodiments for ESD protection. According to one embodiment, an ESD protection circuit comprising four parasitic BJTs may be configured to protect the I/O pads or the power rail. More BJTs or resistors may be used to increase the current paths for ESD stress currents. Several variations and modifications may be made by changing the doping profiles of the doped regions.

Abstract: A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Abstract: A Bi-CMOS semiconductor device and method for manufacturing the same are provided. An n-well can be formed in a semiconductor substrate, and an NMOS transistor can be provided on the substrate separated from the n-well by a device isolation layer. An NPN bipolar transistor can be formed using the n-well. In particular, a collector contact region and a p-base region can be provided in the n-well. In addition, a base contact region and an emitter contact region can be disposed in the p-base region. A silicide is provided on the source and drain regions and the gate of the NMOS transistor, and the base contact region of the NPN bipolar transistor.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a first metal-oxide-semiconductor (MOS), a second MOS, a first semiconductor region, and a second semiconductor region. The first and the second MOSs are formed on the substrate. The first semiconductor region is formed between the substrate and the first MOS. The second semiconductor region is formed between the substrate and the second MOS. The first semiconductor region and the second semiconductor region isolate the first MOS from the second MOS.

Abstract: A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second conductivity type opposite to said first conductivity type, in the semiconductor substrate; forming a base region of the second conductivity type in the collector region; forming first and second insulated gate structure on said first and second wells, and a junction protection structure having same constituent elements as said insulated gate structures on said base region; and forming second source/drain regions of the first conductivity type in said second well, and an emitter region of the first conductivity type in the base region, simultaneously, with an emitter-base junction reaching the principal surface below said junction protection structure.

Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.

Abstract: NPN and PNP bipolar junction transistors are formed in a semiconductor substrate material in a double polysilicon CMOS process flow in a manner that allows the collectors of both of the npn and pnp bipolar transistors to be biased differently than the bias that is placed on the semiconductor substrate material.

Abstract: An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.

Abstract: A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 ?m; an outermost metal film; and a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film so that false judgment of chip quality based on leakage current measurements during manufacturing is reduced particularly when dust is present and skews leakage current measurements due to strain on the wafer and the piezoelectric effect produced.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.