Complementary Transistors In Wells Of Opposite Conductivity Types More Heavily Doped Than The Substrate Region In Which They Are Formed, E.g., Twin Wells Patents (Class 257/371)
  • Patent number: 10504799
    Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
  • Patent number: 10388575
    Abstract: A method for fabricating a semiconductor structure includes providing a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region; forming a first work function layer on the first region, the transition region, and the second region; removing a first portion of the first work function layer formed in the transition region; forming a hard mask layer on the base substrate in the transition region and on the first work function layer in the second region; removing a second portion the first work function layer formed in the first region using the hard mask layer as an etch mask; removing the hard mask layer; and forming a second work function layer, on the base substrate in the first region and the transition region, and on the first work function layer in the second region.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 20, 2019
    Assignees: Semiconductor Manufacturing International (Shaghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10269783
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a cell having a first region designated for a first type of implant and a second region designated for a second type of implant that is different than the first type of implant. The integrated circuit may include a first implant structure configured to implant the first region with the first type of implant such that the first region extends within a portion of the second region. The integrated circuit may include a second implant structure configured to implant the second region with the second type of implant such that the second region extends within a portion of the first region.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 23, 2019
    Assignee: ARM Limited
    Inventors: Abhilash V. Thazhathidathil, Denil Das Kolady, Anand Dhanalakshmi Ramdass
  • Patent number: 10269665
    Abstract: A semiconductor device and a method of fabricating the same are disclosed. A semiconductor device according to an embodiment of the present invention includes: a first type doped semiconductor substrate; a second type doped deep well configured such that one or more semiconductor device elements are formed therein; a first type doped first well formed inside a region surrounded by the deep well of the one surface of the semiconductor substrate, and separated from the semiconductor substrate by the deep well; a first electrical contact formed on a part of the one surface of the semiconductor substrate, and electrically connected to the first well; and a second electrical contact formed on another surface of the semiconductor substrate.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 23, 2019
    Assignee: Seoul National University R&DB Foundation
    Inventors: Jin Hong Ahn, Young June Park
  • Patent number: 10269646
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10211094
    Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 19, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
  • Patent number: 10193553
    Abstract: The invention concerns a circuit comprising: a processing circuit (102) comprising a plurality of circuit domains (103), each circuit domain (103) comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit (104) configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit (104) being further configured to cause said transistor biasing voltages to be applied to the circuit domains.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 29, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Daniele Jahier Pagliari, Edith Beigne, Yves Durand, Massimo Poncino
  • Patent number: 10170574
    Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
  • Patent number: 10096704
    Abstract: A semiconductor device includes a plurality of compensation regions of a vertical electrical element arrangement, a plurality of drift regions of the vertical electrical element arrangement and a non-depletable doping region. The compensation regions of the plurality of compensation regions are arranged in a semiconductor substrate of the semiconductor device. Further, the plurality of drift regions of the vertical electrical element arrangement is arranged in the semiconductor substrate within a cell region of the semiconductor device. The plurality of drift regions and the plurality of compensation regions are arranged alternatingly in a lateral direction. The non-depletable doping region extends laterally from an edge of the cell region towards an edge of the semiconductor substrate. The non-depletable doping region has a doping non-depletable by voltages applied to the semiconductor device during blocking operation.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 10062695
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer modified by the doping with the strain modulator is different from an effective lattice constant of the dielectric layer prior to the doping.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chi Tsai, Kang-Min Kuo
  • Patent number: 10062704
    Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Tzu Yin Chiu, Clifford Ian Drowley, Leong Tee Koh, Yu Lei Jiang, Da Qiang Yu
  • Patent number: 10050035
    Abstract: A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Shao Cheng, Shin-Yeu Tsai, Chui-Ya Peng, Kung-Wei Lee
  • Patent number: 9972682
    Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-chen Yeh
  • Patent number: 9923017
    Abstract: A monolithic active pixel radiation detector including a method of fabricating thereof. The disclosed radiation detector can include a substrate comprising a silicon layer upon which electronics are configured. A plurality of channels can be formed on the silicon layer, wherein the plurality of channels are connected to sources of signals located in a bulk part of the substrate, and wherein the signals flow through electrically conducting vias established in an isolation oxide on the substrate. One or more nested wells can be configured from the substrate, wherein the nested wells assist in collecting charge carriers released in interaction with radiation and wherein the nested wells further separate the electronics from the sensing portion of the detector substrate. The detector can also be configured according to a thick SOA method of fabrication.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 20, 2018
    Assignee: Fermi Research Alliance, LLC
    Inventor: Grzegorz W. Deptuch
  • Patent number: 9911730
    Abstract: A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 6, 2018
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Fei Yao, Shijun Wang
  • Patent number: 9887147
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 6, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Patent number: 9853115
    Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 26, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
  • Patent number: 9843322
    Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
  • Patent number: 9831134
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Patent number: 9748270
    Abstract: The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Juergen Faul
  • Patent number: 9735261
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
  • Patent number: 9716171
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device includes forming a first and a second gate electrode on a semiconductor substrate, forming a first and a second insulator on the first and second gate electrodes, forming a third insulator on the second insulator, a first thickness of the third insulator on the first gate electrode being different than a second thickness of the third insulator on the second gate electrode, and etching-back the first, second and third insulators to form a first spacer beside the first gate electrode and a second spacer beside the second gate electrode. Herein, a horizontal length of the first spacer being contacted with a surface of the semiconductor substrate is different from a horizontal length of the second spacer being contacted with a surface of the semiconductor substrate.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 25, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Gukhwan Kim, Boseok Oh
  • Patent number: 9698047
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Patent number: 9698786
    Abstract: Aspects of the present disclosure are directed to detecting and powering external circuits via a common port. As may be implemented in accordance with one or more embodiments, an accessory detection circuit detects a type of an external circuit based upon a pull-down resistance at an interface port (e.g., where each accessory type provides a discernable pull-down resistance). Power switching circuitry couples power between the interface port and an internal power-based circuit, and operates in an open condition when the accessory detection circuit is active. An adaptive biasing circuit sets a voltage across the power switching circuitry to about zero, based on a voltage level provided on the interface port, thereby mitigating changes in the pull-down resistance due to current leakage. Once the type of external circuit is identified, the power switching circuitry couples power between the external circuit and the internal circuit.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 4, 2017
    Assignee: Nexperia B.V.
    Inventors: Madan Mohan Reddy Vemula, Harold Hanson
  • Patent number: 9601212
    Abstract: A storage device and an information processing method are provided. The storage device has a first power supply unit and at least one first storage cell. The at least one first storage cell stores first data which are associated with a number of charges within the first storage cell. The first power supply unit is electrically connected to the at least one first storage cell. The storage device further has a first control unit configured for controlling the first power supply unit to supply power to the at least one first storage cell according to a predetermined policy, so that the number of charges within the first storage cell satisfies a first preset condition.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: March 21, 2017
    Assignees: BEIJING LENOVO SOFTWARE LTD., LENOVO (BEIJING) LIMITED
    Inventors: Honglei Zhang, Xiaohui Xie, Zhigang Li
  • Patent number: 9553091
    Abstract: A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Ching-Yi Hsu, Jun-Wei Chen
  • Patent number: 9515163
    Abstract: One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 6, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Shom Ponoth, Balasubramanian Pranatharthiharan
  • Patent number: 9502419
    Abstract: A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region, wherein the fin line is wrapped by a first gate electrode structure to form a first transistor and an end of the fin line is of a tapered shape.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9502530
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Grant
    Filed: November 8, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Patent number: 9484422
    Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
  • Patent number: 9484255
    Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: November 1, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
  • Patent number: 9455195
    Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Chang, Katsunori Onishi, Jian Yu
  • Patent number: 9431251
    Abstract: A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Chou Tseng, Chien-Chih Ho
  • Patent number: 9424923
    Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Yasuyuki Takahashi
  • Patent number: 9406601
    Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 2, 2016
    Inventors: Robert P. Masleid, James B. Burr, Michael Pelham
  • Patent number: 9384962
    Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
  • Patent number: 9379058
    Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Zhongze Wang, Ohsang Kwon, Kern Rim, John Jianhong Zhu, Xiangdong Chen, Foua Vang, Raymond George Stephany, Choh Fei Yeap
  • Patent number: 9362309
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9349652
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee, Jung-Piao Chiu
  • Patent number: 9349823
    Abstract: Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Kisik Choi
  • Patent number: 9293478
    Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 22, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hee-Jung Yang, Hyung-Tae Kim, Jae-Young Jeong, Gyu-Won Han, Dong-Sun Kim, Won-Joon Ho
  • Patent number: 9230963
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 9202879
    Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles W. Koburger, III, Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang
  • Patent number: 9147677
    Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 29, 2015
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Javier Alejandro Salcedo, David J Clarke, Jonathan Glen Pfeifer
  • Patent number: 9147695
    Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 29, 2015
    Assignee: STMICROELECTRONICS SA
    Inventors: Frédéric Hasbani, Eric Remond
  • Patent number: 9123427
    Abstract: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: September 1, 2015
    Assignee: III HOLDINGS 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 9076863
    Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Takehito Tamura, Binghua Hu, Sameer Pendharkar, Guru Mathur
  • Publication number: 20150145058
    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.
    Type: Application
    Filed: February 5, 2015
    Publication date: May 28, 2015
    Inventor: Mahalingam Nandakumar
  • Patent number: 9013915
    Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 21, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hirofumi Tokita
  • Publication number: 20150102420
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA