Complementary Transistors In Wells Of Opposite Conductivity Types More Heavily Doped Than The Substrate Region In Which They Are Formed, E.g., Twin Wells Patents (Class 257/371)
  • Publication number: 20120211842
    Abstract: A semiconductor body comprising a first connection for feeding an upper supply potential and a first and a second terminal cell, which are situated at a distance from each other. The semiconductor body further comprises an arrester structure, which is arranged between the first and second terminal cells in a p-doped substrate. The arrester structure comprises a first and a second p-channel field-effect transistor structure, each of which is set in a respective n-doped well substantially parallel to the first and second terminal cells, and a diode structure with a p-doped region set in a further n-doped well between the n-doped wells of the first and second p-channel field-effect transistor structures. The diode structure is designed to activate the first and second p-channel field-effect transistor structure as arrester elements during an electrostatic discharge in the semiconductor body.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 23, 2012
    Applicant: austriamicrosystems AG
    Inventors: Wolfgang REINPRECHT, Frederic Roger
  • Patent number: 8247873
    Abstract: A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the semiconductor substrate, and first side walls (103a, 120a) formed on the side surface of the first gate electrode 102a, and the second MISFET includes a second gate insulating film 101b and a second gate electrode 102b formed on the second region of the semiconductor substrate 100, and second side walls (103b, 120b) formed on the side surface of the second gate electrode 102b. The width of the first side wall is smaller than the width of the second side wall, and the second side wall includes the second spacer 103b containing a higher concentration of hydrogen than the first spacer 103a.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: August 21, 2012
    Assignee: Panasonic Corporation
    Inventor: Shinji Takeoka
  • Patent number: 8237230
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongyean Oh, Woon-kyung Lee
  • Publication number: 20120181620
    Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.
    Type: Application
    Filed: July 9, 2010
    Publication date: July 19, 2012
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala, Chih Sieh Teng, Chin-Miin Shyu
  • Patent number: 8217459
    Abstract: A distance “a” from a first gate electrode of a first transistor of a high-frequency circuit to a first contact is greater than a distance “b” from a second electrode of a second transistor of a digital circuit to a second contact. The first contact is connected to a drain or source of the first transistor, and the second contact is connected to a drain or source of the second transistor.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: July 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Kuramoto, Yasutaka Nakashiba
  • Patent number: 8198687
    Abstract: A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: June 12, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Mark Rinehimer
  • Patent number: 8178930
    Abstract: A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region of second conductivity type (in the case of a high voltage MOS transistor) or in the lightly doped drain (LDD) region of second conductivity type (in the case of a low voltage MOS transistor). Such structure leads to higher on-breakdown voltage. The inventive principle applies to MOS transistors formed on bulky semiconductor substrate and MOS transistors formed in silicon-on-insulator configuration.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 15, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shen-Ping Wang, Tsung-Yi Huang, Wen-Liang Wang
  • Patent number: 8174049
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Goto
  • Patent number: 8148785
    Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: April 3, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaharu Yamaji, Akio Kitamura
  • Publication number: 20120061768
    Abstract: According to an embodiment, a power amplifier is provided with at least one first growth ring gate structure and multiple second growth ring gate structures. The first growth ring gate structure is bounded by a semiconductor layer and performs a power amplification operation. The multiple second growth ring gate structures are bounded by the semiconductor layer and are arranged adjacently around the first growth ring gate structure in a surrounding manner. When the first growth ring gate structure performs a power amplification operation, the multiple second growth ring gate structures are depleted by applying a reverse bias to the multiple second growth ring gate structures whereby the depleted multiple second growth ring gate structures isolate the first growth ring gate structure from a surrounding portion.
    Type: Application
    Filed: March 17, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tadahiro SASAKI, Kazuhide Abe, Atsuko Iida, Kazuhiko Itaya
  • Patent number: 8129793
    Abstract: A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Okamoto
  • Patent number: 8120058
    Abstract: A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jae-Eun Park, Xinlin Wang, Xiangdong Chen
  • Publication number: 20120038003
    Abstract: A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals.
    Type: Application
    Filed: July 22, 2011
    Publication date: February 16, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Toshikatsu Kawachi
  • Patent number: 8110878
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 8101969
    Abstract: In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: January 24, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francine Y. Robb, Stephen P. Robb
  • Patent number: 8102007
    Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: January 24, 2012
    Assignee: Synopsys, Inc.
    Inventors: John D. Hyde, Miguel E. Figueroa, Todd E. Humes, Christopher J. Diorio, Terry D. Hass, Chad A. Lindhorst
  • Patent number: 8097923
    Abstract: A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Thanas Budri, Jiankang Bu
  • Publication number: 20120001268
    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate.
    Type: Application
    Filed: September 9, 2011
    Publication date: January 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, Andres Bryant, Mark D. Jaffe, Alain Loiseau
  • Patent number: 8076957
    Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Isoda
  • Patent number: 8068157
    Abstract: An image sensor includes a photoelectric converter, a source-follower transistor, and a selection transistor. The photoelectric converter generates electric charge in response to received light, and the electric charge varies a voltage of a detection node. The source-follower transistor is coupled between the detection node and an output node and has a first threshold voltage. The selection transistor is coupled between the source-follower transistor and a voltage node with a power supply voltage or a boosted voltage applied thereon, and has a second threshold voltage with a magnitude that is less than a magnitude of the first threshold voltage such that the source-follower transistor operates in saturation.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Il Jung, Min-Young Jung
  • Patent number: 8053373
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 8053844
    Abstract: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Dureseti Chidambarrao
  • Patent number: 8053306
    Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: November 8, 2011
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.
    Inventors: Rick Carter, Michael P. Chudzik, Rashmi Jha, Naim Moumen
  • Patent number: 8053301
    Abstract: Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Jaeger, Michael V. Aquilino, Christopher V. Baiocco
  • Publication number: 20110266631
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
  • Publication number: 20110266632
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 3, 2011
    Inventors: Reika ICHIHARA, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: 8049283
    Abstract: Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 1, 2011
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Do Hyung Kim, Yong Gyu Lim
  • Publication number: 20110248354
    Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.
    Type: Application
    Filed: February 11, 2010
    Publication date: October 13, 2011
    Applicant: Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences
    Inventors: Deyuan Xiao, Xi Wang, Miao Zhang, Jing Chen, Zhongying Xue
  • Patent number: 8030711
    Abstract: A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Nakajima
  • Patent number: 8022446
    Abstract: A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: September 20, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Hua Huang, Kuo-Ming Wu, Yi-Chun Lin, Ming Xiang Li
  • Patent number: 8013395
    Abstract: The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventor: Naoki Kotani
  • Patent number: 8008733
    Abstract: Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 30, 2011
    Assignee: Sony Corporation
    Inventor: Masakatsu Nakai
  • Patent number: 8008748
    Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: David S. Collins, Robert M. Rassel, Eric Thompson
  • Patent number: 8008724
    Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Haining Yang, Huilong Zhu
  • Patent number: 8004047
    Abstract: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 23, 2011
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: 7999327
    Abstract: In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 16, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Akinao Kitahara
  • Patent number: 7999323
    Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri, Keith Kwong Hon Wong
  • Patent number: 7994584
    Abstract: A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabsuhiki Kaisha Toshiba
    Inventors: Takayuki Hiraoka, Kuniaki Utsumi, Tsutomu Kojima, Kenji Honda
  • Patent number: 7989912
    Abstract: The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second compressive stress greater than the first compressive stress. A gate structure is disposed over the active region between the neighboring upper device isolation structures.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 2, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Yun Yl
  • Publication number: 20110180881
    Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo Pinto, Frank S. Johnson
  • Patent number: 7986014
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Publication number: 20110175173
    Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.
    Type: Application
    Filed: January 17, 2011
    Publication date: July 21, 2011
    Inventors: MASATAKA TAKEBUCHI, Kazuhiro Utsunomiya, Noriyasu Ikeda
  • Patent number: 7982271
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20110169099
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuyuki NAKANISHI
  • Patent number: 7974103
    Abstract: A signal transfer member for a liquid crystal display (LCD) apparatus includes a power line for receiving power from an external source and for driving a semiconductor chip disposed on the transfer member or the display apparatus. The power line is bent so as to incorporate a serpentine structure, which enables the length of the power line to be easily adjusted and results in the line being longer than a power line formed with a relatively straight structure. Accordingly, the length of the power line can be adjusted to take into account the respective impedances of the chip and the external source so as to suppress electromagnetic waves in the power line. This prevents the creation of noise, distortion of signals, damage to the semiconductor chip, and disconnection of the input interconnection thereof that are caused by the electromagnetic waves, so that product yields are thereby improved.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myong-Bin Lim, Jae-Han Lee, Sun-Kyu Son, In-Yong Hwang
  • Patent number: 7968947
    Abstract: This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b).
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: June 28, 2011
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Patent number: 7968910
    Abstract: A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Thomas W. Dyer, Haining S. Yang
  • Patent number: 7968921
    Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 7964460
    Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: June 21, 2011
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: RE42776
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do