Abstract: An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate dielectric layer on the substrate and forming a gate electrode on the gate dielectric layer with a lower surface, a midpoint, and a quantity of p-type impurity. A quantity of nitrogen is introduced into the gate electrode whereby the quantity nitrogen has a peak concentration proximate the lower surface. A quantity of germanium is introduced into the gate electrode and first and second source/drain regions are formed in the substrate. The method enables simultaneous formation of n-channel and p-channel gate electrodes with work functions tailored for both types of devices.

Abstract: A power DMOS transistor having an improved current driving capability and improved reliability is provided. A fabrication method thereof is also provided. The DMOS transistor includes a semiconductor substrate having a first conductivity type and a semiconductor region having a second conductivity type formed on the semiconductor substrate. A drain having a second conductivity type is formed on the semiconductor region. A high-concentration buried impurity layer having a second conductivity type is formed on the semiconductor region under the drain. A body region having a first conductivity type is formed in the semiconductor substrate spaced a predetermined distance from the semiconductor region. A source having a second conductivity type is formed on the body region. A gate electrode is formed on the semiconductor substrate having a gate insulative film formed thereon. A source electrode and a drain electrode coupled respectively to the source and the drain are formed on the resultant structure.

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: Disclosed is a semiconductor device capable of increasing the operational speed and reducing the power consumption. The semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor which are provided on a common base-substrate. A surface region, in which the n-channel field effect transistor is provided, of the base-substrate includes: a silicon substrate; a buffer layer formed on the silicon substrate, the buffer layer being made from a silicon-germanium compound having a germanium concentration gradually increased toward an upper surface of the buffer layer; a relax layer formed on the buffer layer, the relax layer being made from a silicon-germanium compound having a germanium concentration nearly equal to that of a surface portion of the buffer layer; and a silicon layer formed on the relax layer. Source/drain regions are formed in the silicon layer.

Abstract: The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42.

Abstract: A semiconductor device can reduce a leak current, and a manufacturing method can provide such a semiconductor device. A semiconductor device includes an isolating and insulating film formed on a main surface of a semiconductor substrate including a first conductivity type region, and also includes a field-effect transistor. The field-effect transistor includes a second conductivity type region neighboring to the isolating and insulating film, a gate electrode, a lower layer side wall film formed on a side surface of the gate electrode, an upper layer side wall film formed on the lower layer side wall film and containing a material different from that of the lower layer side wall film, and a high-melting-point metal silicide layer formed on the second conductivity type region.

Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: A CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contract region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.

Abstract: In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Abstract: An electronic switch in integrated circuit from includes a first n-channel MOS transistor and a second n-channel MOS transistor with respective source-drain paths in series between an input terminal and an output terminal, and a third n-channel MOS transistor connected between a connection node between the first and second transistors and a supply terminal. The gate electrodes of the first and second transistors are connected together to a first control terminal and the gate electrode of the third transistor is connected to a second control terminal of the electronic switch. The first and third transistors are formed in a first p-well and the second transistor is formed in a second p-well, insulated from the first. A circuit branch which is identical, but provided by p-channel MOS transistors is also provided between the input and output terminals.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: An MOS capacitor is provided in the proximity of the boundary between a P well and an N well formed of a bottom N well and an N well. Accordingly, the proximity of the boundary corresponding to the so-called dead space can be used effectively.

Abstract: The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.

Abstract: A complementary Field Effect Transistor includes a first transistor and a second transistor stacked on the first transistor. The angle between the source/drain pair for the first transistor and the source/drain pair for the second transistor is nonzero and other than 180 degrees (e.g., 90 degrees). In one embodiment, each transistor has its own gate, and the active regions for the transistors are separated and situated between the gates. In another embodiment, the active regions for the transistors share a single channel region. In still another embodiment, the transistors share a single gate. In yet another embodiment, the transistors share both a channel region and a gate.

Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104).

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: A laser trimming link is provided on a field oxide film. An N well is formed below the field oxide film and in the surface of a semiconductor substrate. N well is formed of a retrograde well.

Abstract: High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Abstract: A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.

Abstract: A semiconductor device comprises a semiconductor layer formed on an insulation layer, a pair of source and drain diffusion layer formed on a surface of the semiconductor layer, a first gate electrode disposed on the semiconductor layer region interposed between the pair of source and drain diffusion layer through a gate insulation film, a substrate potential control layer coupled to the semiconductor layer in a region interposed between the pair of the source and drain diffusion layer and formed in such a manner that the first gate electrode does not exist thereon, and a second gate electrode disposed to be in contact with the first gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a well region of a first conductivity type formed; a well region of a second conductivity type; a trench isolation region; a source region and a drain region of the first conductivity type; a channel region formed; a gate insulating film; and a gate electrode being electrically connected to the well region of the second conductivity type, wherein the product &tgr;, i.e.

Abstract: A CMOS arrangement is described which has at least one NMOS region (2) and at least one PMOS region (3) and which is provided at its surface with substrate contacts (24, 34), via which it is possible to apply predetermined voltage values to respective substrate sections (1, 30) of the CMOS arrangement. The CMOS arrangement described is distinguished by the fact that the average number of substrate contacts (24, 34) per unit area and/or the average substrate contact area per unit area within the at least one NMOS region (2) is significantly smaller than within the at least one PMOS region (3).

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A Bi-CMOS semiconductor device having a CMOS device region and a bipolar transistor region is provided wherein the bipolar transistor has a collector region of a first conductivity type and the CMOS region has at least one element region of a second conductivity type which is positioned adjacent to the collector region as well as wherein a single buried layer of the first conductivity type is provided which extends under the element region of the CMOS region and the collector region.

Abstract: A MOS field effect transistor device and fabrication method thereof are provided, which include a non-uniformly doped well region composed of (1) a first portion thereof which is contiguous to a source or drain region, and situated under a gate electrode, and has a first concentration of said first conductive type impurities, and (2) a second.sub.-- portion which has a second concentration higher than the first concentration of said first conductive type impurities. This structure of the field effect transistor has advantages such as, for example, suppressing short channel effects, increasing source or drain junction breakdown voltages and improving high frequency characteristics of the transistor.

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.

Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

Abstract: A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type. A first well of a second conductivity type is disposed in the semiconductor substrate. A second well of the first conductivity type is disposed in the first well. A third well of the second conductivity is disposed in the second well. A MOS transistor having a source region and a drain region of the first conductivity type is disposed in the third well.

Abstract: A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

Abstract: A semiconductor device with reduced number of through holes is disclosed. A source region and a dielectric layer are connected by a conductive layer made of silicide formed on the surface of the source region and the dielectric layer commonly, and a drain region and an output electrode are connected by another conductive layer made of silicide. The conductive layer interconnecting the source region and the dielectric layer, and the conductive layer interconnecting the drain region and the output electrode are formed in one step as they are disposed beneath an insulation layer on the surface of the semiconductor substrate.

Abstract: A semiconductor device including a substrate (220) having a primary surface, a memory cell (202) provided on the substrate, the memory cell (202) including a P-channel transistor, the P-channel transistor having an N-type gate (72), and peripheral portion (204) provided on the substrate, the peripheral portion including a P-channel transistor , the P-channel transistor having a P-type gate (99). A method for forming the semiconductor device is also disclosed.

Abstract: An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: In a semiconductor apparatus comprises a signal input portion having an amplifying circuit including one, two or more insulating gate type transistors (MIS Tr), one MIS Tr or at least one (M1) of the two or more MIS Trs of the signal input portion is an MIS Tr of one conductivity channel type. The MIS Tr (M1) of the one conductivity channel type is formed in a semiconductor region which is electrically isolated from the other MIS Tr (M3) of one conductivity channel type provided for a circuit portion other than the signal input portion, so that an input threshold level of the signal amplifying circuit is made coincide with a DC level of the input signal, thereby preventing an erroneous operation.

Abstract: An MOS transistor with high voltage sustaining capability and low closing resistance comprises a substrate (10) provided with a doping of a first conductive type, and a well area (20) formed in the substrate (10) and provided with a doping of a second conductive type opposite to the first conductive type. Further, the MOS transistor comprises source and drain areas (26,28) of the first conductive type formed in the well area (20). The MOS transistor is provided with a gate (32) comprising a gate oxide layer (36) and arranged between the source region (26) and the drain area (28), the gate (32) having drain-side end region (42) arranged at a distance (40) from the drain area (28). The MOS transistor comprises a drain extension region (24) provided with a doping of the first conductive type and having the drain area (28) arranged therein, with the drain extension region (24) reaching below the drain-side end region (42) of the gate (32).

Abstract: An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.

Abstract: A CMOS device includes first and second wells formed in first and second regions of a semiconductor substrate, respectively. First and second transistors are formed in the respective wells. A third transistor is formed in a third region of the semiconductor substrate outside of the wells. A first impurity layer is formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer, deeper than the first impurity layer, is formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without requiring any additional, separate mask processing steps.

Abstract: A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of the insulated gate semiconductor devices is controlled by using the difference in work function between the gate electrode and the active layer. The present semiconductor device has excellent uniformity and reproducibility.

Abstract: A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.

Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: A square measure of a basic cell and a basic circuit cell of a semiconductor device used a SOI.cndot.CMOS technology is reduced. In the semiconductor device used a SOI.cndot.CMOS technology, the basic cells constituted by two pieces of PMOS and two pieces of NMOS are arranged in order of the PMOS, the PMOS, the NMOS and NMOS or NMOS, the NMOS, the PMOS and the PMOS in a row, and the diffused layer of a portion on which the PMOS and the NMOS adjoin are formed in a manner to adjoin directly. Moreover, the power source wiring and the grounding wiring are arranged around the basic cell in a manner to being held in common with the adjacent cells, and at least one of PMOS diffused layers is arranged so as to be able to be connected with a power source wiring through a contact directly and at least one of NMOS diffused layers is arranged so as to be able to be connected with a grounding wiring through a contact directly.

Abstract: An oxidation layer 44 for masking is formed on a PNP type transistor formation region 46a together with a field oxidation layer 42 for device separation. The oxidation layer 44 for masking is formed so as to cover an upper part of an active base formation region 52a located between the emitter/collector formation region 50a. The upper part of the active base formation region 52a which is not possible to adjust impurity concentration at processes carried out later is covered with the oxidation layer 44 for masking being formed relatively thick when boron B is implanted into a PMOS type transistor formation region 48a as channel ion. So that, boron is not implanted ionically to the active base formation region 52a. Therefore, it is not necessary to carry out masking process using photo resist layer in prior to boron implantation process.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.