Abstract: A semiconductor device is provided and contains a semiconductor substrate, a first transistor, and a second transistor. The first transistor is formed on the semiconductor substrate and has a first gate electrode. The second transistor is formed on the semiconductor substrate and has a second gate electrode. Also, the thickness of the first gate electrode is different than the thickness of the second gate electrode. Also, a method for forming the semiconductor device is provided.

Abstract: A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)<V.sub.ths -V.sub.tha, where V.sub.DD represents the higher voltage among the two stationary values.

Abstract: A 6-T SRAM cell having a MOS transistor with source/drain regions having an absence of heavily doped portions characteristic of prior art lightly doped drain (LDD) MOS devices is fabricated. Forming the MOS transistor with an absence of heavily doped portions of source/drain regions allows the width of the MOS gate layer, the width of the MOS source/drain regions and the width of the field oxide region between active regions of the SRAM cell to be reduced compared to the prior art. Accordingly, the present SRAM cell occupies less chip area than a prior art SRAM cell. Further, forming the MOS transistor without heavily doped portions of source/drain regions improves latch-up immunity and decreases write cycle time of the present SRAM cell.

Abstract: Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first conductivity type in the first well region. To improve the electrical characteristics of circuits within the memory device, a first semiconductor device is provided in the first sub-well region (which is biased at a back-bias potential (Vbb)) and a second semiconductor device is provided in the second sub-well region (which is biased at a ground or negative supply potential (Vss)). The first semiconductor device is preferably selected from the group consisting of memory cell access transistors, equalization circuits and isolation gates. The second semiconductor device is also preferably selected from the group consisting of column select circuits and sense amplifiers.

Abstract: A CMOS integrated circuit device enabling accurate inspection of its static power source current includes: a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of the p-channel MOS transistor; a second pad connected to the source of the n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well having formed the p-channel MOS transistor; an n-type diffused region formed in the p-type substrate or p-well having formed the n-channel MOS transistor; a third pad connected through the p-type diffused region to the n-type substrate or n-well having formed the p-channel MOS transistor; and a fourth pad connected through the n-type diffused region to the p-type substrate or p-well having formed the n-channel MOS transistor.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: A semiconductor device with an alignment mark has a first well of a first conductivity type formed on the entire surface of a semiconductor substrate, a second well of a second conductivity type opposite to the first conductivity type formed within a desired region of the first well, and an oxide film formed on said first well and said second well, the first well having a higher impurity concentration than that of the semiconductor substrate, the depth of the first well being greater than that of said second well, and the oxide film having a step-wise alignment mark at a boundary between the first well and the second well.

Abstract: The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region.

Abstract: A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Abstract: A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

Abstract: A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.

Abstract: A semiconductor device includes a source and a drain formed in a device region of a semiconductor substrate, and an electrode withdrawal portion having an impurity concentration higher than that of the device region. The electrode withdrawal portion is formed so as to adjoin either one of the source and drain. An electrode for the source or drain adjacent to the electrode withdrawal portion is used jointly as an electrode for the electrode withdrawal portion.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the specific embodiment of the present invention, the n+ diffused source bus regions and the nearby p+ well tap may: (a) be separately tied to the Vss metal common source line through separate contact metals (e.g., tungsten plugs); (b) be butted against each other and tied to a common Vss metal source line through separate contact metals; (c) be butted against each other and tied to a common Vss metal source line through a common contact metal (e.g.

Abstract: A method of making a plug transistor is disclosed. The method includes providing a semiconductor substrate with an active region of a first conductivity type, providing a doped layer of a second conductivity type in the active region, forming a dielectric layer over the active region, forming an opening in the dielectric layer, implanting a dopant of the first conductivity type through the opening into a portion of the doped layer beneath the opening thereby counterdoping the portion of the doped layer and splitting the doped layer into source and drain regions, forming a gate insulator on the active region and in the opening, and forming a gate on the gate insulator and in the opening and adjacent to the dielectric layer. Preferably, a single photoresist layer provides an etch mask for the dielectric layer and an implant mask for the dopant.

Abstract: A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region.

Abstract: A method for producing a semiconductor configuration, such as a field plate insulating transistor, is suitable for providing mutual insulation of two complementary wells in a substrate. A first insulation layer, a dopable layer and a sacrificial layer are applied on the substrate. A first region of the sacrificial layer is removed to form an edge through the use of a first mask technique, and a first region of the dopable layer which is thereby bared is doped simultaneously with the substrate located beneath, creating the first well. The second well is produced analogously, with the edge serving as an adjustment mark for a requisite second mask technique. It is not until after the doping that a second insulation layer is applied, which is then structured to form the insulating transistor.

Abstract: A semiconductor device and fabrication thereof is disclosed in which devices are formed on two devices regions of opposite conductivity types by selectively masking and implanting the same type of dopant into active regions of both device regions. The process includes masking part of the active regions in each device region and implanting a dopant into exposed active regions in both devices regions. The number of masking, implantation and other steps required in the fabrication process are reduced by the selective masking of various active regions. Non-symmetrically doped source and drain regions may be formed on the transistors among a group which lie closest to the opposite device region.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: A method of fabricating a semiconductor device. The procedure of fabricating process is performed inversely as the conventional method. Less numbers of photolithography process is performed with the application of selective liquid phase deposition.

Abstract: A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.

Abstract: The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.

Abstract: An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip with a plurality of parallel CMOS devices therein, particularly a plurality of NMOS devices arranged as parallel N-P-N bipolars. In the MOSFET circuits, a number of sets of cooperating N+ regions are deposited in a P-well in a P-type substrate to form, with electrodes and connections, a set of parallel source-base-drain transistors. The ESD pass voltage is effected by different processes due to the current-crowding effect. The current distribution in each of the N-P-N bipolars is strongly dependent on the P-well resistivity so that to reduce the current crowding effect and render the current distribution uniform in each parallel N-P-N bipolar, an additional P-well implantation is used to reduce the P-well resistivity in the input, I/O, and output buffer ESD protection circuits. Accordingly, the effective protection width will be increased and the ESD performance is improved.

Abstract: An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer.

Abstract: A semiconductor memory device operable under a first power voltage and a second power voltage which are different from each other. The memory device includes a substrate of a first conductivity type, a well of a second conductivity type defined in said substrate, and first and second inverter circuits defined serially with one another on the substrate and common well. The first inverter circuit includes a first transistor of a second conductivity type on the substrate and a first transistor of a first conductivity type on the well for receiving a first power voltage and generating a first inverted output voltage in response to a first input voltage applied to gates of the respective first transistors.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.

Abstract: An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.

Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

Abstract: A substrate region of an n-channel MOS transistor is supplied with a bias voltage (VNBL) lower than a ground voltage (Vss) in a standby cycle, and with a bias voltage (VNBH) higher than the ground voltage in an active cycle. The difference between an internal power supply voltage (intVcc) and the bias voltage (VNBL) is at the level of a driving voltage (VPP) transmitted to a selected word line, while the arithmetic mean of the bias voltages (VNBL, VNBH) is substantially at the level of the ground voltage. A back gate voltage can be generated by a MOS transistor having gate insulating film breakdown voltage of the same degree as that of a memory cell transistor. Reliability of the gate insulating film of the MOS transistor of a back gate voltage generation circuit is improved, and the back gate voltage is readily generated on-chip.

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract: Integrated circuits having built-in electrostatic discharge protection thyristors include a semiconductor substrate with well regions of predetermined conductivity type therein which enable the formation of pairs of built-in thyristors which provided overvoltage protection. The substrate preferably contains first and second well regions of first and second conductivity type, respectively, at spaced locations, and third and fourth well regions of second and first conductivity type, respectively, which form respective P-N junctions with the first and second well regions. A first pair of guard regions of opposite conductivity type is also formed in the third well region, and this first pair of guard regions is electrically coupled to a first reference potential. In addition, a second pair of guard regions of opposite conductivity type is formed in the fourth well region and this pair of guard regions is electrically connected to a second reference potential.

Abstract: A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided.

Abstract: A single level gate NVM device (10) includes p-channel and n-channel floating gate FETs (12, 14), an erasing capacitor (26), and a programming capacitor (28). The NVM device (10) is programmed by applying a programming voltage to the programming capacitor (28) and applying a ground voltage to the sources of the FETs (12, 14). The NVM device (10) is erased by applying an erasing voltage to the erasing capacitor (26) and applying ground voltage to the sources of the FETs (12, 14) and to the programming capacitor (28). Data is read from the NVM device (10) by sensing a voltage level at the drains of the FETs (12, 14) while applying a logic high voltage to the source of the p-channel FET (12), a logic low voltage to the source of the n-channel FET (14), and a reading voltage to the programming capacitor (28).

Abstract: A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the device channel region, and a gate insulator separating the device gate and channel region. The first and second diffusion regions are electrically connected to a positive power supply, and the device gate is electrically connected to a negative power supply. The decoupling capacitor may be formed proximate a signal driver in the integrated circuit. The decoupling capacitor may be formed without additional, expensive semiconductor fabrication steps and operates to minimize noise in the circuit.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A field-effect transistor structure is described having a monocrystalline silicon channel region which is epitaxially continuous with an underlying monocrystalline silicon body region. Polycrystalline silicon source and drain regions abut the channel region. The source and drain regions are electrically isolated from the underlying body region by a patterned dielectric layer, which may include a thick field oxide. A polycrystalline silicon gate is capacitively coupled with the channel region by a second dielectric layer. The gate may extend laterally to partly overlap the source and drain regions.

Abstract: A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.

Abstract: A semiconductor device to which two kinds of electric voltage can be supplied comprises: a first MOS transistor formed in the first well having a first conduction type and being fixed to a first electric potential, a second MOS transistor formed in a second well having a second conduction type different from the first one and being fixed to a second electric potential higher than the first electric potential, and a third well formed between the first and second wells having the second conduction type and being fixed to a ground electric potential. The first MOS transistor comprises a first gate oxide film having a prescribed thickness and a first gate electrode having a prescribed gate length, while the second MOS transistor comprises a second gate oxide film having a thickness larger than the prescribed thickness of the first gate oxide film and a second gate electrode having a gate length longer than the prescribed thickness of the first gate length.

Abstract: N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

Abstract: A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

Abstract: A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract: There are disclosed a semiconductor device and a method for fabrication thereof. The semiconductor device comprises an insulating film for well isolation which electrically insulates N-well from P-well, the drain electrode of PMOS and the drain electrode of NMOS being adjacent to the trench fox well isolation, and a conductive wire filling one contact hole which interconnects the drain electrodes of N-well with those of P-well. The semiconductor device is very reduced in size, and thus, high integration thereof can be achieved.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A semiconductor memory device is provided that can have the memory cell size reduced and electrical imbalance eliminated. This semiconductor memory device has gate electrodes of a driver transistor and a load transistor formed of a first polysilicon layer, and a word line also serving as a gate electrode of an access transistor formed of a different layer of a second polysilicon layer. Therefore, the gate electrodes of the driver transistor and the load transistor can be overlapped with each other in a planar manner with the word line, resulting in reduction in the planar area of the memory cell. In a cell current path, a contact portion other than a bit line contact and a GND contact is not provided. Therefore, electrical imbalance in memory cells is prevented.

Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized.