Abstract: A semiconductor device and a signal processing system having a metal oxide semiconductor (MOS) transistor with a silicon-on-insulator (SOI) structure are provided. The semiconductor device and the signal processing system include a main MOS transistor and an assistance MOS transistor. The main MOS transistor includes a first gate interconnection for receiving an external signal, first source/drain regions of a first conductivity type, and a body. The assistance MOS transistor includes a second gate interconnection and second source/drain regions of a second conductivity type opposite to the first conductivity type. The assistance MOS transistor selectively floats or grounds the body according to the external signal. The first gate interconnection and the second gate interconnection are electrically connected to each other by an interconnection layer.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: First and second circuit blocks are provided in a semiconductor device. The first circuit block is provided with a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor. The second circuit block is provided with a second complementary MOS transistor including a second P-channel MOS transistor and a second N-channel MOS transistor. The threshold voltages of the first P-channel MOS transistor and the first N-channel MOS transistor are set to be higher than those of the second P-channel MOS transistor and the second N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in a stand-by state is set to be substantially equal to that of the first P-channel MOS transistor.

Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: A horizontal, insulated gate field effect transistor of the present invention includes a semiconductor substrate of first conductivity. A well region of second conductivity is formed on the surface of the semiconductor substrate. A source region of first conductivity is formed in the well region. A source electrode is connected to the source region. A drain region of first conductivity is formed in the well region. A gate dielectric is formed on the well region and extends over the source region and drain region. A gate electrode is formed on the gate dielectric. The drain electrode is connected to the well region at a position other than the drain region.

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

Abstract: A method for fabricating a semiconductor device comprises implantating and diffusing a first well in a semiconductor substrate. A second well is implantated and diffused in the first well. A third well is implantated in the second well and a MOS transistor is formed in the third well.

Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Abstract: In a semiconductor memory device, first and second impurity regions of a second conductivity are provided as wells in a semiconductor substrate of a first conductivity. Outside of the first and second impurity regions, third impurity regions of the first conductivity are provided as wells in the substrate. Fourth impurity regions of the first conductivity are provided as wells in the first impurity regions. The first impurity regions each have an impurity concentration which gradually decreases with increasing depth below the top surface of the semiconductor substrate, and the fourth impurity regions have at least two impurity concentration peaks below the top surface of the semiconductor substrate. A memory cell can be reliably erased by forming a retrograde pocket well for a memory cell array, and a diffusion well surrounding the pocket well, thus maintaining a high breakdown voltage between the pocket well and the substrate.

Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N− LDS/LDD regions in the P-well. Form N− LDS/LDD regions in the P-well and P− lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N− LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P− LDS/LDD regions in the N-well in the source/drain sites.

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

Abstract: A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the semiconductor substrate. The second well isolates the semiconductor substrate and the first well from each other. Phosphorus ions for forming the bottom of the second well are implanted into the semiconductor substrate more deeply than boron ions for forming the first well. The depths to which these ions are implanted can be varied by acceleration energy of the ions. If the ions are so implanted, the total sum of impurities constituting the second well can be decreased within the surface area of the first well.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate, improving the self-resonance frequency of inductors and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices, such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: A semiconductor device is fabricated by injecting fluorine into a region of a semiconductor substrate other than a region of the semiconductor substrate where a thinnest gate insulating film is to be formed, among a plurality of regions where gate insulating films are to be formed. Then, the semiconductor substrate with fluorine injected therein is oxidized to form an oxide film in the plurality of regions. A surface of the oxide film is nitrided to turn a surface layer thereof into an oxynitride film or form a nitride film on the surface of the oxide film. The semiconductor device has a plurality of gate insulating films of different thicknesses which contain nitrogen in their surface layers.

Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: The present invention is envisioned to realize miniaturization, low voltage operation and high reliability of a nonvolatile semiconductor memory device, and simplification of its production process. Interpoly dielectric film 109a of the nonvolatile semiconductor memory device is composed of a nitrogen-introduced CVD SiO2 film, and is used as gate oxide film of MOS transistors in the low voltage region of the peripheral circuit region. Gate oxide film of MOS transistors in the high voltage region of the peripheral circuit region is composed of a laminate of said SiO2 film 109a and a nitrogen-introduced CVD SiO2 film. According to the present invention, reliability of gate oxide film of peripheral circuit MOS transistors of the nonvolatile semiconductor memory device and its transistor characteristics are improved. It is also possible to realize miniaturization and low voltage operation of the nonvolatile semiconductor memory device. Further, simplification of its production process is made possible.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: A CMOS semiconductor device comprises a P-substrate, an N-type shallow well for forming a PMOS transistor and a P-type shallow well for forming NMOS transistor, which are selectively formed in a surface region of the P-substrate, a leading region for the N-type shallow well and a leading region for the P-type shallow well, STI regions for separating the CMOS transistor formed in a surface region of the P-substrate and positioned between the drain region of the PMOS transistor and the drain region of the NMOS transistor and between the N-type shallow well and the P-type shallow well, the STI regions being formed deeper than the shallow wells, and an STI region for isolating the CMOS region formed in a surface region of the P-substrate, the STI region being formed deeper than the shallow wells.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: A mixed-signal integrated circuit device comprises a digital circuitry portion (DIGITAL) including digital circuitry (10) and an analog circuitry portion (ANALOG) including analog circuitry (14). The digital circuitry produces plural first digital signals (T1-Tn). The analog circuitry produces one or more analog signals (OUTA, OUTB) in dependence upon received second digital signals (TCK1-TCKn). The device also comprises a signal control circuitry portion (LATCH) including signal control circuitry which derives the second digital signals (TCK1-TCKn) from the first digital signals (T1-Tn) and controls the timing of application of the second digital signals to respective inputs of the analog circuitry. To avoid jitter in the second digital signals arising from power supply loading changes, power is supplied independently to each of the circuitry portions (DIGITAL, LATCH and ANALOG).

Abstract: An objective of the present invention is to realize a comparator which uses MOS transistors and has a reduced offset voltage and occupies a small surface area. This is characterized in that an impurity is introduced into a channel region of a MOS transistor, the mobility of a load side MOS transistor is made smaller than the mobility of a differential side MOS transistor, and the mutual conductance of the load side MOS transistor is made smaller than the mutual conductance of the differential side MOS transistor.

Abstract: A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface.

Abstract: An electrical circuit for measuring threshold voltages and also a circuit for controlling threshold value variations, while avoiding a need to significantly modify or alter the circuit layout, are provided. A semiconductor device has a plurality of substrate conductor regions commonly shared by multiple metal insulator semiconductor field effect transistors (MISFETs) of the same conductivity type, wherein each of the plurality of substrate conductor regions is electrically separated or isolated from one another.

Abstract: A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Abstract: A method of manufacturing a semiconductor device which has the steps of: forming an insulated gate field effect transistor of a first conductivity type on a semiconductor substrate; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere; and forming a capacitor upper electrode on the dielectric oxide film.

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: A complementary MOS semiconductor device comprising: a complementary MOS logic circuit having a plurality of field effect transistors; a first wiring and a second wiring as a source for supplying therethrough a power source voltage to the complementary MOS logic circuit; a first power supply circuit for controlling the supply of the power source voltage from said first wiring to said complementary MOS logic circuit; a second power supply circuit for controlling the supply of the power source voltage from said second wiring to said complementary MOS logic circuit; and a third power supply circuit for controlling the operation of said first power supply circuit, wherein said third power supply circuit includes field effect transistors each having a gate insulating film with 2.5 nm or more thickness.

Abstract: A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

Abstract: An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory-metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A high-voltage element (H)to which a high gate voltage is applied, and a low-voltage element (L) to which a low gate voltage is applied, are formed in a semiconductor substrate (1). Bird's beaks (8, 18) are formed in gate insulating films (7, 17) by thermal oxidation. Since a gate electrode (9) of the element (H) has a shorter gate length than a gate electrode (19) of the element (L), the ratio of the bird's beak in the gate insulating films (7, 17) is small in the element (L) and large in the element (H). Therefore, the element (H) has a high breakdown voltage and less aged deterioration, leading to long lifetime. The element (L) has a high current driving capability to produce high-speed operation. Thus, long lifetime, high operation speed and easy manufacturing steps are realized at the same time.

Abstract: A high-voltage electrostatic discharge protection circuit according to the invention has the following structure. A first high-voltage N-well region, a first high-voltage P-well region, a second high-voltage N-well region and a second high-voltage P-well region are adjacent to each other. A PMOS transistor is formed on the first high-voltage N-well region and has its source electrically connected to a high voltage and its drain electrically connected to an input/output pad. A first isolation region is formed between the first high-voltage N-well region and the first high-voltage P-well region and electrically connected to the drain of the PMOS transistor. A first N+-type region is formed between the first high-voltage P-well region and the second high-voltage N-well region, adjacent to the first isolation region and electrically connected to the input/output pad.

Abstract: One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

Abstract: CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a way that they block and dissipate the erroneous signal. The added transistor structures are made immune to SEU by placing them in well diffusions that are separate from the rest of the circuit and biasing those wells such that the electric fields surrounding the transistors are very low in comparison to the rest of the circuit. Signal blocking is achieved with an SEU immune transistor that is in an “off” state whenever other circuit transistors that deliver signals through it are potentially sensitive to SEU. Dissipation is achieved with either a resistor or low current drive transistor that spreads the SEU signal out over time thereby reducing its voltage change to an acceptable level.

Abstract: A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).