Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Abstract: A dual-gate CMOS semiconductor device and a manufacturing method therefor suppressing mutual diffusion of P type impurities and N type impurities in a gate electrode are provided. This invention is comprised of an NMOS part 103 and a PMOS part 104 formed on a semiconductor substrate; a polycrystalline silicon layer formed on the NMOS part 103 and the PMOS part 104 and consisting of an N type impurity containing polycrystalline silicon layer 106 and a P type impurity containing polycrystalline silicon layer 107; and a first conductive layer 108 formed on the polycrystalline silicon layer so as to include a groove region 120, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer 106 and the P type impurity containing polycrystalline silicon layer 107.

Abstract: To solve the problem that when a high temperature heat treatment is avoided, a substrate leak current increases due to the interfacial level generated with a plasma damage and thereby clearness of the CMOS image sensor is deteriorated. There is provided a CMOS image sensor characterized in using an epitaxial wafer as an element substrate, and more particularly to a CMOS image sensor characterized in that a tungsten layer is formed after formation of a contact hole used for connection between the elements in the element substrate and wirings and after the tungsten layer is removed from the area other than the contact hole, the annealing is conducted under the nitrogen and hydrogen atmosphere or under the hydrogen atmosphere.

Abstract: A high voltage protection circuit (20) in a non-volatile memory includes a first transistor (22) and a second transistor (24) each formed in their own separate wells. A high voltage supply (Vhv) is provided at the drain of the second transistor (24). The source (40) of second transistor (24) is connected to the drain of first transistor (22) and to well (32), and the gate of the second transistor (24) is connected to Vdd, the main power supply to the chip. By forming the transistors in their own separate wells with the source of the second transistor (24) connected to its own well, breakdown of the circuit is governed by the sum of BVdss of the first transistor (22) and a gate induced breakdown (BVind) of the second transistor (24). With this circuit use of even a low Vdd (e.g. <3V) on the gate of the second transistor (24) is sufficient to protect against unwanted exposure to Vhs or to prevent leakage so that a higher stand-off voltage need not be generated and routed to the circuit.

Abstract: In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.

Abstract: An integrated CMOS semiconductor circuit comprises: an internal circuit composed of CMOS transistors including P3- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit composed of any electrical element and provided with a power source; and a switch portion which is enable to apply, in the standby state in the internal circuit, a reverse bias between the source and the substrate of either one of the P- and N-channel transistors of the internal circuit by the power source of the external circuit.

Abstract: The present invention contemplates a highly reliable semiconductor memory device. The semiconductor memory device includes a silicon substrate containing a p impurity of a first concentration, an epitaxial layer formed at the silicon substrate and containing a p impurity having a second concentration lower than the first concentration, a memory region provided on the epitaxial layer, and a logic circuit region provided on the epitaxial layer at a location different from the memory region. The memory region includes a p well, an n well and a bottom well. The logic circuit region includes a complementary field effect transistor.

Abstract: An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. The drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. The drain of an another PMOS transistor and the gate of still another PMOS transistor are connected to the first node. The drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacitance and drain capacitance of these PMOS transistors is appended to the two nodes.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation. Consequently, with a semiconductor device of the CMOS structure, it is possible to prevent unwanted creeping of silicide that occurs often in the shallow junction region depending on a concentration of an impurity having a low diffusion coefficient as represented by arsenic. Further, not only can the resistance in the shallow junction region be lowered, but also an amount of overlaps can be optimized in each transistor.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: A semiconductor device which has complementary logic gates, including: a field effect transistor 101 having a first conductivity type channel, a first conductivity type well region 202 formed on a semiconductor substrate 102, a second conductivity type channel layer 203 formed on the surface of the region 202, a first wire 112 that connects an end 204 of the second conductivity type channel layer 203 to a first conductivity type drain region 106, a second wire 208 that connects the other end 205 of the second conductivity type channel layer 203, and a third wire 208 that connects the first conductivity type well region 202 to a second power source that has the same polarity as a first power source; and manufacturing method thereof. This semiconductor device and manufacturing method enables low power consumption and simple control of threshold voltage values as well as avoiding increases in the number of manufacturing processes.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Abstract: A new class of electronic systems, wherein microelectronic semiconductor integrated circuit devices are integrated on a common substrate with molecular electronic devices.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

Abstract: An Si1−yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterounction junction is formed between the Si and Si1−yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si1−yGey layer can be suppressed. As a result, the Si/Si1−yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.

Abstract: An integrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50),(140) and drain regions (55),(145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70),(80) serve as the drain extension regions of the transistors.

Abstract: A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).

Abstract: The present invention is intended to provide a semiconductor device having a gate electrode free from increasing of resistance of the gate electrode, from decreasing of capacitance of the insulation film due to depletion, and from penetrating of impurity. The semiconductor device comprises a silicon layer, a gate insulating film formed on the silicon layer, a metal boron compound layer formed on the gate insulating film, and a gate electrode formed on the metal boron compound layer and containing at least silicon.

Abstract: A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

Abstract: When an arsenic ion (As+) large in mass is injected, polysilicon films are covered with a fifth resist mask so as to cover an end of the resist mask covering the polysilicon films to form a PMOS forming region. Through this process, a silicide non-forming region is arranged not to overlap with a pn junction to prevent the silicide non-forming region from increasing in resistance.

Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device may have a significant relative gain and is constructed with no additional mask steps.

Abstract: A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

Abstract: A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between Vdd and circuit ground to form a first inverter with a first data node (1) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (2) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node (1) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation.

Abstract: An insulated gate N-channel field effect transistor has a P-type semiconductor substrate, an N-type epitaxial layer disposed on the P-type semiconductor substrate, and a gate insulating film disposed on the N-type epitaxial layer. An N-type high concentration source region is formed in the N-type epitaxial layer. An N-type high concentration drain region is formed in the epitaxial layer in spaced-apart relation to the N-type high concentration source region. A channel forming region is disposed between the N-type high concentration source region and the N-type high concentration drain region. A gate electrode is formed on the channel forming region through the gate insulating film. An N-type low concentration region is disposed between the N-type high concentration drain region and the channel forming region and between the N-type high concentration source region and the channel forming region. An insulating film is disposed on the low concentration region.

Abstract: The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

Abstract: The present disclosure relates that by modifying the masking layer normally utilized for complimentary type tub development to provide one or more additional openings arranged in close proximity to the drain area of a selected power device of the non-complimentary type, that the dopant profile may be modified to provide a greater voltage breakdown exclusively for that selected power device without affecting similar type logic circuit non-complimentary devices as found within the same integrated circuit chip. Furthermore, this is accomplished without the need for providing an additional mask or additional process steps to supplement and thereby disturb a given predefined process set for the fabrication of semiconductor devices.

Abstract: The present disclosure relates that by modifying the masking layer normally utilized for complimentary type tub development to provide one or more additional openings arranged in close proximity to the drain area of a selected power device of the non-complimentary type, that the dopant profile may be modified to provide a greater voltage breakdown exclusively for that selected power device without affecting similar type logic circuit non-complimentary devices as found within the same integrated circuit chip. Furthermore, this is accomplished without the need for providing an additional mask or additional process steps to supplement and thereby disturb a given predefined process set for the fabrication of semiconductor devices.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

Abstract: A process of manufacturing a semiconductor device having a dual gate CMOS transistor in which an nMOS transistor in the dual gate CMOS transistor is formed by the steps of: (a) forming a gate insulating film and a silicon film on a semiconductor substrate; (b) implanting n-type impurities into the silicon film in an nMOS region of the semiconductor substrate; (c) forming a conductive film on the silicon film; and (d) patterning the silicon film and the conductive film into a gate electrode.

Abstract: Disclosed herein is a semiconductor device wherein element active regions for an N channel region and a P channel region are formed so as to adjoin each other, and gate electrode is formed so as to stride over both channel regions and an element isolation oxide film for separating both channel regions from each other. In the semiconductor device, the gate electrode comprises a structure wherein a polycrystalline silicon film, a first barrier metal film, a second barrier metal film and a metal film are laminated in order from below. The first barrier metal film is removed at the border part between the N channel region and the P channel region.

Abstract: A charge pump formed in a silicon-on-insulator (SOI) substrate is disclosed. The charge pump comprises a SOI layer formed on a substrate. Formed in the silicon of the SOI is a first p-body and a second p-body. Also formed in the silicon is a n+ region that extends down to the insulator so that the n+ region separates the first p-body and second p-body. Finally, a gate structure is formed atop of a portion of the first p-body and a portion of the n+ region. The gate structure is separated from the 1st p-body and n+ region by gate oxide, and it serves as charge pump capacitor. Both the diode turn-on (when gate is pulsing high and forward biasing the p-body to n+ junction), and GIDL current (when the gate is pulsing low, and generates GIDL hole currents from n+ surface to p-body) will result in a “short” of the p-body and n+ region; this ensures the proper operation of charge pump.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region . P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract: An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a barrier film in a field region of the semiconductor substrate, first and second conductivity-type well regions in the semiconductor substrate and divided by the barrier film in a surface of the semiconductor substrate, a gate insulating film on an entire surface of the semiconductor substrate, a gate electrode on a region of the gate insulating film, a lightly-doped first conductivity-type impurity region formed in the second conductivity-type well region at a first side of the gate electrode, a lightly-doped second conductivity-type impurity region formed in the first conductivity-type well region at a second side of the gate electrode, a conductive pattern connected with the lightly-doped first and second conductivity-type impurity regions and having a constant distance from the gate electrode, an insulating film formed on the semiconductor substrate exposing upper portions of the gate electrode and the conductive pattern, and heavily-doped first

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Abstract: This invention provides a semiconductor device having stable characteristics of break down voltage and on resistance and the like. More specifically, this invention provides a semiconductor device comprising: a P-type semiconductor layer; an N-type first well formed on the surface of the semiconductor layer; a P-type second well formed on the surface of the first well; an N-type source region formed on the surface of the second well; an N-type drain region formed on the surface of the first well and formed apart from the source region at a specific distance; a gate electrode formed on the semiconductor layer and extending from the source region to the second well and the first well; an application electrode arranged apart from the gate electrode, arranged on the first well between the second well and the drain region and extending from the first well to the edge thereof; and a P-type first impurity diffusion layer formed on the surface of the second well and reaching the second well under the source region.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.