Abstract: A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.

Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor.

Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with a much lower dielectric constant, or forming holes within the dielectric layer by filling the upper parts of the holes. The inter-level dielectric layer in such a structure has a much lower dielectric constant, reduces RC delay between devices of integrated circuits and also is easy to integrate; besides, since the holes within the dielectric layer are non-interconnected, they shall not cause change to the dielectric constant of the dielectric material or a short circuit between wires, thus the device shall have better stability and reliability which then improve performance of the circuit.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

Abstract: An array substrate and a display apparatus including the array substrate are provided. The array substrate includes a substrate divided into a display area and a peripheral area adjacent to the display area. A pixel array is formed on the substrate corresponding to the display area and receives a driving signal. A driving circuit includes a plurality of stages and is formed on the substrate corresponding to the peripheral area. Each of the stages includes a first transistor having a source electrode connected to an output terminal to output the driving signal, a channel layer formed between a gate insulating layer and the source electrode, the channel layer having an opening to facilitate contact between a portion of the gate insulating layer and the source electrode, and a capacitor defined by a gate electrode of the first transistor, the source electrode, and the gate insulating layer contacting the source electrode.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: A method for producing a silicon substrate, including the steps of providing a silicon substrate having an essentially planar silicon surface, producing a porous silicon surface having a plurality of pores, in particular having macropores and/or mesopores and/or nanopores, applying a filling material that is to be inserted into the silicon, which has a diameter that is less than a diameter of the pores, inserting the filling material into the pores and removing the excess filling material form the silicon surface, if necessary, and tempering the silicon substrate that is furnished with the filling material that has been filled into the pores, at a temperature between ca. 1000° C. and ca. 1400° C., in order to close the generated pores again and to enclose the filling material.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract: A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

Abstract: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown directly on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown directly on the lower electrode.

Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.

Abstract: A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

Abstract: A semiconductor device includes a semiconductor substrate having a first portion and a second portion and a first transistor of a first type formed in the first portion of the substrate, the first transistor being operable at a first voltage, and the first transistor including a doped channel region of a second type opposite of the first type. The semiconductor device also includes a second transistor of the second type formed in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage, the second transistor including an extended doped feature of the second type. Further, the semiconductor device includes a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit.

Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.

Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.

Abstract: An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.

Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A MEMS transducer includes a substrate, a membrane layer and a back-plate layer. The membrane layer is supported by the substrate. The back-plate layer is supported by the membrane layer and includes a respective sidewall portion and a respective raised portion. One or more columns, separate from the sidewall portion of the back-plate layer, connect the back-plate layer, the membrane layer and the substrate.

Abstract: An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs.

Abstract: A recessed channel transistor includes an isolation layer provided in a semiconductor substrate to define an active region. A trench is provided in the semiconductor substrate to extend across the active region. A gate insulation layer covers a sidewall and a bottom face of the trench and an upper face of the semiconductor substrate adjacent to an upper edge of the trench, wherein a portion of the gate insulation layer on the upper surface of the semiconductor substrate adjacent to the upper edge of the trench and on the sidewall of the trench extending to a first distance downwardly from the upper edge of the trench has a thickness greater than that of a portion of the gate insulation layer on the remaining sidewall and the bottom face of the trench. A gate electrode fills up the trench having the gate insulation layer formed therein.

Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.