In Vertical-walled Groove Patents (Class 257/397)
  • Patent number: 10748807
    Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Torsten Helm, Marc Probst, Uwe Rudolph
  • Patent number: 10741547
    Abstract: A semiconductor device includes: a first conductivity-type semiconductor substrate; a second conductivity-type base region provided on a front surface side inside the semiconductor substrate, a gate trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the gate trench portion having a gate conductive portion, and a dummy trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the dummy trench portion including an upper dummy conductive portion having an emitter potential and a lower gate conductive portion positioned below the upper dummy conductive portion and having a gate potential, wherein the lower gate conductive portion of the dummy trench portion is connected to the gate conductive portion of the gate trench portion.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10699938
    Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Patent number: 10539846
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 21, 2020
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Patent number: 10505023
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate, and forming a mask layer covering the first fin structure and the second fin structure. The method also includes performing a first etching operation using the second fin structure as an etch stop layer to partially remove the mask layer such that the etch stop layer protrudes from the mask layer after the first etching operation. The method further includes partially removing the second fin structure using a second etching operation after the first etching operation.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 10340346
    Abstract: A semiconductor device includes a drain layer, a drift layer, a base region, a source region, trenches, base contact region, gate regions, and field plate electrodes. The drain layer extends in a first and a second direction. The drift layer is on the drain layer. The base region is on the drift layer. The source region is on the base region. The trenches are in an array and each trench reaches the drift layer from the source region. The base contact region is along the second direction in a region in which the trenches do not contiguously exist along the second direction and electrically connects the source region to the base region. Each gate regions is along an inner wall of the trenches. Each field plate electrodes is in an inside of the gate regions and is longer than the gate regions in the third direction.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Kenya Kobayashi
  • Patent number: 10224395
    Abstract: In an element isolation region defining an element formation region, there is formed an element isolation unit including an element isolation unit and the other element isolation unit. The other element isolation unit is arranged in a direction intersecting a direction in which the element isolation unit extends from the element isolation unit. The element isolation unit includes a sidewall oxide film formed in a trench, a titanium film, a titanium nitride film, and a tungsten film. The tungsten film is formed to cover the bottom surface of a trench in the element isolation unit and to close an opening end of a trench in the other element isolation unit. A plug is formed in contact with the tungsten film of the element isolation unit.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuki Yokota
  • Patent number: 10170413
    Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Yusuke Oniki, Hidehiro Fujiwara
  • Patent number: 10164090
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 25, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10153163
    Abstract: Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Sangwon Kim, Seongjun Park
  • Patent number: 10128304
    Abstract: A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-I Hsu, Min-Feng Kao, Jen-Cheng Liu, Dun-Nian Yaung, Tzu-Hsuan Hsu, Wen-De Wang
  • Patent number: 10103256
    Abstract: A semiconductor device, including a first groove, a second groove and a first impurity region provided on a semiconductor substrate, a second impurity region provided in the first impurity region, a gate electrode provided in the first groove, a first insulating film provided between the first groove and the gate electrode, a second insulating film provided in the second groove, and a third insulating film provided astride tops of the first groove and the second groove. Each of the first and second insulating films has a lower half portion that is thicker than an upper half portion thereof. The lower half portions of the first and second insulating films are connected. The gate electrode has first and second portions thereof respectively contacting the lower and upper half portions of the first insulating film, a width of the first portion being narrower than a width of the second portion.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 16, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei
  • Patent number: 10096700
    Abstract: A power semiconductor device includes a semiconductor substrate, trench structures comprising a first, a second, a third and a fourth trench structure formed in the substrate, a second conductivity type body region formed between the trench structures, a first conductivity type source region formed in the second conductivity type body region, and an emitter electrode and a gate pad formed over the substrate, wherein each trench structure includes a top electrode and a bottom electrode, and each top electrode is insulated from the corresponding bottom electrode, and wherein the first trench structure is symmetric to the fourth trench structure, and the second trench structure is symmetric to the third trench structure, and wherein the first trench structure is not identical to the second trench structure, and wherein no first conductivity type source region is formed to be adjacent to the second trench structure and the third trench structure.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 9, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kwang Ho Na, Seung Wook Song, Yong Hun Kim
  • Patent number: 10074556
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masaaki Shinohara, Shigeo Tokumitsu
  • Patent number: 10062773
    Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 28, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Kadoshima, Masao Inoue
  • Patent number: 10049913
    Abstract: Methods for void-free SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO2 film until the recessed features are filled with SiO2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO2 material form shallow trench isolation (STI) structures in a semiconductor device.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 9812394
    Abstract: An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li, Werner A Rausch
  • Patent number: 9805984
    Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Chen Kuang-Hsin
  • Patent number: 9721794
    Abstract: Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Sangwon Kim, Seongjun Park
  • Patent number: 9711409
    Abstract: A fin arrangement and a method for manufacturing the same are provided. An example method may include: patterning a substrate to form an initial fin on a selected area of the substrate; forming, on the substrate, a dielectric layer to substantially cover the initial fin, wherein a portion of the dielectric layer located on top of the initial fin has a thickness substantially less than that of a portion the dielectric layer located on the substrate; and etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion of the initial fin is used as a fin.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 18, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 9666672
    Abstract: A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin. A sidewall of the first dielectric layer has a dip-shape profile. A second dielectric layer is disposed along sidewalls of the first fin. A top surface of the second dielectric layer is substantially coplanar with the top surface of the first fin. A second fin includes a second semiconductor material different from the first semiconductor material. An isolation region is disposed between the first fin and the second fin.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Chin-Chi Wang
  • Patent number: 9576956
    Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 21, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 9385191
    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Patent number: 8958246
    Abstract: A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M?1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 17, 2015
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Fang Yuan
  • Patent number: 8901720
    Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 2, 2014
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Michael Brennan, Scott Bell
  • Publication number: 20140346612
    Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8866234
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Woo Young Chung
  • Publication number: 20140291770
    Abstract: The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 2, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Chen Kuang-Hsin
  • Patent number: 8829643
    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Zailong Bian, Janos Fucsko
  • Patent number: 8823091
    Abstract: The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Kyu tae Kim
  • Patent number: 8785275
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Patent number: 8748959
    Abstract: A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I Koldiaev, Jungtae Kwon, Pierre C. Fazan
  • Patent number: 8716791
    Abstract: Semiconductor devices, such as LDMOS devices, are described that include a plurality of trench regions formed in an extended drain region of the devices. In one or more implementations, the semiconductor devices include a substrate having an extended drain region, a source region, and a drain region, all of the first conductivity type, formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow charge carriers (e.g., majority carriers) to travel between the source region and the drain region. A plurality of trench regions are formed within the extended drain region that are configured to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: May 6, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Farshid Iravani, Timothy K. McGuire
  • Patent number: 8692352
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: 8686492
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: April 1, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Patent number: 8680624
    Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 25, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Man Fai Ng, Bin Yang
  • Patent number: 8664707
    Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 4, 2014
    Assignees: Samsung Electronics Co., Ltd., The Regents of the University of California
    Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
  • Patent number: 8592918
    Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
  • Publication number: 20130277759
    Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 8530306
    Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 10, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8525273
    Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-kyum Kwon, Tae-jung Lee, Sun-hyun Kim
  • Patent number: 8497173
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 30, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Young Chung
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8450810
    Abstract: An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 28, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Yasuhiro Takeda
  • Patent number: 8436419
    Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: May 7, 2013
    Assignee: DENSO CORPORATION
    Inventors: Akira Yamada, Nozomu Akagi
  • Patent number: 8426926
    Abstract: A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongsuk Shin, Dong Hyuk Kim, Myungsun Kim, YongJoo Lee, Hoi Sung Chung
  • Patent number: 8377785
    Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventor: Thomas W. Dyer
  • Patent number: 8362576
    Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 29, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 8357989
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: RE46773
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii