Abstract: The semiconductor device disclosed has semiconductor patterns as elements constituting a semiconductor device on a semiconductor substrate. The semiconductor patterns are formed respectively on a first region and a second region on the semiconductor substrate. Between the first region and the second region, there is a stepped portion which is set such that a value S of the step is S=m.lambda./2n wherein .lambda. is a wavelength of the photosensitive illuminating light used in a photolithography process for patterning a photoresist film, m is a positive integer, and n is a refractive index of the photoresist film. The provision of the stepped portion enables the formation of semiconductor element patterns of fine sizes with controllability thereof.

Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: A semiconductor device includes at least one passive device and is configured such that parasitic capacitances associated with the passive device are minimized. A substrate layer of the semiconductor device is formed of a substrate material characterized by a first dielectric constant. The substrate layer has at least one deep trench formed therein, and the deep trench is filled with a trench fill material characterized by a second, effective, dielectric constant that is lower than the first dielectric constant. A field layer is formed on a surface of the substrate layer over the deep trench. Finally, the passive device is formed on a surface of the field layer.

Abstract: A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same.The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

Abstract: The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

Abstract: Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions.

Abstract: A graduated concentration profile is used for defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.

Abstract: A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

Abstract: In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction.

Abstract: The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part.Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.

Abstract: A dielectrics dividing wafer is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern extending laterally parallel to a face surface of the wafer, and partition dielectric films, in the form of vertical walls extending from the face surface and the rear surface of the wafer, to the embedded dielectric films, are provided to define semiconductor areas extending continuously from the face surface of the wafer to the rear surface of the wafer. The semiconductor areas can be used for vertical circuit elements. The partition dielectric films in conjunction with the embedded dielectric films and the face surface of the wafer also define additional planar semiconductor areas that can be used for planar structure circuit elements.

Abstract: It is the object of this invention to improve the breakdown voltage between the source and the drain of a MOS transistor having radiation resistance. A high concentration impurity having the same polarity as that of the source-drain region is formed below a gate oxide film at both ends in the channel width direction of the source-drain region of the MOS transistor. An impurity region having the same polarity as that of the source-drain region and an impurity concentration lower than that of the source-drain region is formed between the high concentration impurity region and the source-drain region.

Abstract: According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.

Abstract: A semiconductor device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate and having a first source diffusion region, a first drain diffusion region and a first gate electrode, a second transistor formed on the semiconductor substrate adjacent to the first transistor and having a second source diffusion region, a second drain diffusion region and a second gate electrode, a field oxide layer formed on the semiconductor substrate for isolating the first and second transistors, a first insulator layer which covers a surface of the semiconductor substrate including a surface of the first transistor but excluding a surface of the second transistor, where the first insulator layer has a side wall portion, and a second insulator layer formed at the side wall portion of the first insulator layer and a side wall portion of the second gate electrode of the second transistor.

Abstract: A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.