Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.

Abstract: A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.

Abstract: An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped charge region.

Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: A nonvolatile semiconductor memory device with a substrate. A plurality of dielectric films and electrode films are alternately stacked on the substrate and have a through hole penetrating in the stacking direction. A semiconductor pillar is formed inside the through hole. A charge storage layer is provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.

Abstract: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric constant insulating film are formed sequentially in this order on one surface of a silicon substrate.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.

Abstract: A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.

Abstract: A semiconductor device includes a semiconductor substrate, and a p-channel MOS transistor provided on the semiconductor substrate, the p-channel MOS transistor comprising a first gate dielectric film including Hf, a second gate dielectric film provided on the first gate dielectric film and including aluminum oxide, and a first metal silicide gate electrode provided on the second gate dielectric film.

Abstract: Thin film transistors and arrays having controlled threshold voltage and improved ION/IOFF ratio are provided in this invention. In one embodiment, a thin film transistor having a first gate insulator of high breakdown field with positive fixed charges and a second gate insulator with negative fixed charges is provided; said negative fixed charges substantially compensate said positive fixed charges in order to reduce threshold voltage and OFF state threshold voltage of said transistor. In another embodiment, a thin film transistor having a first passivation layer with negative fixed charges is provided, the negative charges reduce substantially unwanted negative charges in the adjacent active channel and hence reduce the OFF state current and increase ION/IOFF ratio, which in turn reduce the threshold voltage of the transistor.

Abstract: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors.

Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.

Abstract: A semiconductor device includes a substrate and a doped hafnium oxide layer disposed on the substrate, the doped hafnium oxide layer including a hafnium oxide layer doped with doping atoms and having tetragonal unit lattices, an ion size of the doping atom being greater than an ion size of a hafnium atom.

Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.

Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.

Abstract: Disclosed herein is a semiconductor device including a gate insulating film formed over a semiconductor substrate, and a gate electrode formed over the gate insulating film, wherein the gate insulating film is so provided as to protrude from both sides of the gate electrode, and the gate electrode includes a wholly silicided layer.

Abstract: A flash memory device includes a tunnel insulating layer formed over a semiconductor substrate, a charge trap layer formed over the tunnel insulating layer and configured to trap electric charges, a blocking insulating layer formed over the charge trap layer, and a gate electrode formed over the blocking insulating layer and including a first conductive layer and a second conductive layer doped with N and P impurities respectively. Further, a method of erasing a flash memory device includes providing a flash memory device including a gate electrode having a first conductive layer and a second conductive layer doped with N and P impurities respectively, and performing an erase operation in a state where a thickness of a depletion layer at an interface of a PN junction comprising the first conductive layer and the second conductive layer is increased due to a negative potential bias applied to the gate electrode.

Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.

Abstract: In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.

Abstract: A semiconductor device and a method of fabricating the same are described. A substrate having a PMOS area and an NMOS area is provided. A high-k layer is formed on the substrate. A first cap layer is formed on the high-k layer in the PMOS area, and a second cap layer is formed on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer. A metal layer and a polysilicon layer are sequentially formed on the first and second cap layers. The polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer are patterned to form first and second gate structures respectively in the PMOS and NMOS areas. First source/drain regions are formed in the substrate beside the first gate structure. Second source/drain regions are formed in the substrate beside the second gate structure.

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-? material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract: A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

Abstract: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.

Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: A semiconductor device is provided which includes a gate electrode (30) provided on a semiconductor substrate (10), an oxide/nitride/oxide (ONO) film (18) that is formed between the gate electrode (30) and the semiconductor substrate (10) and has a charge storage region (14) under the gate electrode (30), and a bit line (28) that is buried in the semiconductor substrate (10) and includes a low concentration diffusion region (24), a high concentration diffusion region (22) that is formed in the center of the low concentration diffusion region (24) and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line (28) and the semiconductor substrate (10).

Abstract: A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.

Abstract: CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.

Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

Abstract: Method of fabricating TFTs (thin-film transistors) having a crystallized silicon film and a gate-insulating film. First, an amorphous silicon film is formed on an insulating substrate. A first dielectric film is formed from silicon oxide on the amorphous silicon film. Holes are formed in the first dielectric film to selectively expose the surface of the amorphous silicon film. Nickel is introduced as the metal element into the amorphous silicon film. The film is heat-treated, thus forming crystallized silicon film. This crystalline silicon film is etched together with the silicon oxide film to form an active layer. The etched silicon oxide film acts as the aforementioned gate-insulating film. Even after the crystallization step, the silicon oxide film is left behind. As a result, the interface with the crystalline silicon film is kept in a good state.

Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.

Abstract: A nonvolatile memory cell is capable of reducing an excessive current leakage due to a rough surface of a polysilicon and of performing even at a low temperature process by forming the first oxide film including a silicon oxynitride (SiOxNy) layer using nitrous oxide plasma and by forming a plurality of silicon nanocrystals in a nitride film by implanting a silicon nanocrystal on the nitride film by an ion implantation method, and a fabricating method thereof and a memory apparatus including the nonvolatile memory cell.

Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A thin film transistor, and a flat panel display with the same, including a gate electrode, source and drain electrodes, an organic semiconductor layer, and a gate insulating layer. A first capacitance is a capacitance at a first point where the organic semiconductor layer, an electrode, and the gate insulating layer contact one another, a second capacitance is a capacitance at a second point where the organic semiconductor layer contacts the gate insulating layer, a third capacitance is a capacitance at a third point where the electrode contacts the gate insulating layer, and a fourth capacitance is a capacitance at a fourth point where the organic semiconductor layer contacts the electrode. The first capacitance is greater than one of the second capacitance, the third capacitance, and the fourth capacitance.

Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.