Abstract: A gate-insulating film of the present invention is a gate-insulating film having a polycrystalline film made of a metal oxide, in which a grain boundary plane extending in parallel with the polycrystalline film is present at the position of a predetermined thickness of the polycrystalline film and grain boundaries extending in the film-thickness direction of polycrystals configuring the polycrystalline film are discontinuous at the grain boundary plane.

Abstract: A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.

Abstract: The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: A semiconductor device (10) has a substrate (20) with a surface (26) for defining a trench (34). A control electrode (45) is disposed at the surface to activate a conduction path (50) along a sidewall (36) of the trench with a control signal (VGATE). A dielectric layer (32, 35) is formed between the sidewall and the control electrode to have a first width (WGS) adjacent to the surface and a second width (WGC) smaller than the first width adjacent to the conduction path.

Abstract: A low junction capacitance semiconductor structure and an I/O buffer are disclosed. The semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed in a semiconductor substrate and has a gate and source and drain region formed aside the gate. The lightly doped region has a conductivity the same as the source and drain regions, and is formed in the drain region and has a depth larger than the source and drain regions. Further, the lightly doped region can be achieved by CMOS-compatible processes, and the formed devices in the well can be isolated from the semiconductor substrate using deeply doped regions which are usually adopted in advanced technologies.

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same. A semiconductor device having first and second transistor regions and a field region includes a semiconductor substrate having a first type conductivity, a first trench in the substrate at the field region separating the first and second transistor regions from each other, a second trench in the substrate over the first trench, a first field oxide layer in the first trench, a second field oxide layer in the second trench over the first field oxide layer, first and second gate oxide layers on sides of the second trench, first and second gates in the second field oxide layer, and second and third impurity regions at the bottom surface of the second trench and first and fourth impurity regions outside the second trench on the substrate.

Abstract: A dual-gate CMOS semiconductor device and a manufacturing method therefor suppressing mutual diffusion of P type impurities and N type impurities in a gate electrode are provided. This invention is comprised of an NMOS part 103 and a PMOS part 104 formed on a semiconductor substrate; a polycrystalline silicon layer formed on the NMOS part 103 and the PMOS part 104 and consisting of an N type impurity containing polycrystalline silicon layer 106 and a P type impurity containing polycrystalline silicon layer 107; and a first conductive layer 108 formed on the polycrystalline silicon layer so as to include a groove region 120, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer 106 and the P type impurity containing polycrystalline silicon layer 107.

Abstract: A semiconductor device includes a Si oxide film formed between a Si substrate and a metallic oxide film is prevented from growing when an annealing treatment is performed after the metallic oxide film is formed, and a method for manufacturing the same. A semiconductor device comprises a silicon substrate, a gate insulating film formed on the silicon substrate and made of the metallic oxide film, and a gate electrode formed on the gate insulating film, wherein an interface film formed between the gate insulating film and the Si substrate is thinner at the ends of the gate insulating film than in the center thereof.

Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.

Abstract: A method is shown for producing a PIN photodiode using a reduced number of masks wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A groove is etched from the second surface of the fabrication substrate through the intrinsic region to the first surface in order to isolate the photodiode.

Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.

Abstract: Provided is an improved fabrication process for a semiconductor device by means of which in fabrication of insulated gate semiconductor devices having gate insulating films including silicon oxide films of different thickness, no contamination from a photoresist is ensured in a silicon oxide film, generation of defects in the silicon oxide film to be otherwise caused by aqueous solution treatments is suppressed, and thereby variability of characteristics among the semiconductor devices is suppressed.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: This invention pertains generally to forming thin aluminum oxides at low temperatures, and more particularly to forming uniformly thick, aluminum gate oxides. We disclose a low temperature method for forming a thin, uniform aluminum gate oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; forming a uniformly thick aluminum layer 13; and stabilizing the substrate at a first temperature. The method further includes exposing the aluminum layer to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, aluminum oxide film 16. This method is suitable for room temperature processing.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in a production line chamber followed by the deposition of a polysilicon layer (22). Following the creation of the gate oxide assembly (10) a pressure of at least 1.2 Torr is maintained while lowering the power within the production line chamber. The invention can be used with a gate oxide layer (16) of less than 1000 angstroms.

Abstract: In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

Abstract: In a silicon substrate, impurity diffusion layers, serving as source and drain regions, are formed to be separated from each other. A gate insulation film is formed on the silicon substrate between these source and drain regions. The gate insulation film is a silicon oxide film containing Cl having concentration of more than 1.times.10.sup.18 atoms/cm.sup.3 and less than 2.times.10.sup.20 atoms/cm.sup.3, and the gate insulation film is formed on the silicon substrate by low-pressure CVD. A gate electrode, formed of a polysilicon layer, is formed on the gate insulation film. An inter-level insulation film is formed on a resultant structure. A contact hole is formed on each of the source and drain regions of the inter-level insulation film. A drain electrode is formed on the inter-level insulation film, and connected to the drain region through the contact hole. A source electrode is formed on the inter-level insulation film, and connected to the source region through the contact hole.

Abstract: A semiconductor device having a cobalt niobate-cobalt silicide gate electrode structure is provided. A semiconductor device, consistent with one embodiment of the invention, is formed by forming a cobalt niobate gate insulating layer over the substrate and forming a cobalt silicide layer over the cobalt niobate layer. The cobalt silicide layer and cobalt niobate gate insulating layer may, for example, be selectively removed to form at least one cobalt silicide-cobalt niobate gate electrode structure. The cobalt niobate-cobalt silicide gate electrode structure can, for example, increase the operating speed of the device as compared to conventional transistors.

Abstract: A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.

Abstract: A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The disposable layer (22) comprises a material that may be removed selectively with respect to silicon and the gate dielectric, such as germanium. If desired, a second dielectric layer (24) may be formed over the disposable layer (22). A pattern (26) is then formed exposing areas (14) of the circuit where a thinner gate dielectric is desired. The second dielectric layer (24), if it is present, and the disposable layer (22) are removed from the exposed areas. The pattern (26) is then removed. Following pre-gate cleaning, the second gate dielectric (30) is formed. The remaining portions of the disposable layer (22) may be removed either prior to, during, or after the second gate dielectric formation (30).

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Abstract: A MOS semiconductor device comprises a semiconductor substrate having source and drain regions, a first insulating film disposed over the substrate in a space overlapping opposed edges of the source and drain regions, and a gate electrode disposed on the first insulating film. A second insulating film is disposed at overlapping portions between the gate electrode and the source and drain regions to prevent the formation of a space therebetween.

Abstract: A semiconductor structure having a temperature sensor placed in close proximity to gate and source and/or drain electrodes. The sensor is compatible with conventional semiconductor processing and is typically made from doped polysilicon having a large temperature coefficient of resistivity. At least one sensor may be placed under, but insulated from, source or drain electrodes to protect against high electric fields. The sensor is also compatible with bipolar semiconductor structures.

Abstract: The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.

Abstract: An Si oxide film, an oriented paraelectric oxide thin film and an oriented ferroelectric thin film are laminated on an Si single crystal substrate having a region for a source and a drain. A conductor thin film is formed in a portion not covered with an insulating film. A laminated structure formed of the Si oxide film, the oriented paraelectric oxide thin film and the oriented ferroelectric thin film is used as a gate of a transistor. The Si oxide film functions as a carrier injection inhibiting layer.

Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.

Abstract: A semiconductor device advantageously has first and second oxidized silicon insulating layers formed on the surface of a substrate. A first oxidized silicon insulating layer is formed through a low temperature process and a second oxidized silicon insulating layer may be formed at a higher manufacturing process temperature. Advantageously, the first oxidized silicon insulating layer has a lower voltage resistance than the second oxidized silicon insulating layer.

Abstract: A gate dielectric layer comprising a carbon film aligned to, and continuously covering, the gate electrode. The carbon dielectric film adheres to a wide variety of gate metals and is readily etched using etch processes which do not etch into the gate metal. In a preferred embodiment, the self-aligned carbon gate dielectric is deposited by plasma deposition, followed by deposition of a redundant gate dielectric.

Abstract: A thin film transistor and method includes a substrate and a first semiconductor layer formed on the substrate. A first insulating layer is formed on the first semiconductor layer, and a doped semiconductor layer is formed on an upper portion of the first semiconductor layer at first and second sides of the first insulating layer. A second insulating layer is formed on the first insulating layer and the doped semiconductor layer, the second insulating layer having contact holes. A gate electrode is formed on a portion of the second insulating layer, and source and drain electrodes are formed on portions of the second insulating layer, the source and drain electrodes contacting the doped semiconductor layer through the contact holes, respectively.

Abstract: A semiconductor device which includes a mesa type silicon film with a source/drain region and a channel region formed therein, a gate oxide film formed on the mesa type silicon film, and a gate electrode provided on the mesa type silicon film through the gate oxide film, wherein an oxide film having a thickness greater than that of the gate film is formed at the top edge section of the mesa type silicon which is present under the gate electrode, as well as a method for manufacturing it.

Abstract: An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery o

Abstract: The semiconductor device has a large capacity of power driving, and can operate at a high speed. A first semiconductor region of a first conductivity type is formed on a metal substrate through a first insulating film. In the first semiconductor region, first source and drain regions of a second conductivity type are formed. Further, on the region which isolates the first source and drain regions, a first metallic gate electrode is formed through a second insulating film.

Abstract: A nonvolatile memory device having a control gate laid over a floating gate via an interlayer insulating layer, wherein the side portions of the floating gate and the control gate have a side wall insulating film doped with phosphorus, whereby the retention of the charges stored at the floating gate is improved, and a process for production of a nonvolatile memory device comprising forming a gate insulating film, a floating gate, an interlayer insulating layer, and a control gate on a semiconductor substrate, then forming a side wall insulating film doped with phosphorus on the semiconductor substrate by chemical vapor deposition and anisotropically etching the side wall insulating layer so as to form a side wall insulating film doped with phosphorus at the side portions of the floating gate and the control gate.

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide.

Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.

Abstract: A semiconductor element including a silicon substrate, a silicon oxide film formed on the silicon substrate, and a top electrode formed on the silicon oxide film, wherein chromium is included only in a region of the silicon oxide film, the region including the interface between the silicon oxide film and the top electrode and the vicinity of the interface, and the method of manufacturing the same.

Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate eiectrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide.

Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.

Abstract: A field-effect transistor comprising a semiconductor substrate having source and drain regions and a gate electrode, wherein a thin organic film including donor and acceptor molecules is provided between the semiconductor substrate and the gate electrode. When a predetermined voltage is applied to the gate electrode, charge transfer occurs between the donor and acceptor molecules included in the thin organic film, thereby controlling the surface potential of the semiconductor substrate.