Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
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Publication number: 20130001708Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.Type: ApplicationFiled: June 22, 2012Publication date: January 3, 2013Inventors: Pierre Caubet, Sylvain Baudot
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Publication number: 20130001706Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Balasubramanian S. Haran, Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Publication number: 20130001707Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
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Patent number: 8344422Abstract: A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0?x?1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0?y?1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.Type: GrantFiled: December 25, 2008Date of Patent: January 1, 2013Assignee: NEC CorporationInventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
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Publication number: 20120326243Abstract: A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum metal layer disposed orderly on the high-k gate dielectric layer, where the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer. Furthermore, the source/drain region is disposed in the substrate at each of two sides of the aluminum metal gate.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Inventors: Hsin-Fu Huang, Chi-Mao Hsu, Min-Chuan Tsai, Chin-Fu Lin, Chun-Hsien Lin
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Publication number: 20120326244Abstract: A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate with being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.Type: ApplicationFiled: July 20, 2012Publication date: December 27, 2012Inventors: Masamichi SUZUKI, Tatsuo Shimizu, Atsuhiro Kinoshita
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Patent number: 8338825Abstract: Disclosed is a substrate-mediated assembly for graphene structures. According to an embodiment, long-range ordered, multilayer BN(111) films can be formed by atomic layer deposition (ALD) onto a substrate. The subject BN(111) films can then be used to order carbon atoms into a graphene sheet during a carbon deposition process.Type: GrantFiled: September 23, 2011Date of Patent: December 25, 2012Assignee: University of North TexasInventor: Jeffry A. Kelber
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Publication number: 20120319214Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Inventors: Cheng-Yu Ma, Wen-Han Hung
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Publication number: 20120319215Abstract: The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly.Type: ApplicationFiled: November 29, 2011Publication date: December 20, 2012Inventors: Guilei Wang, Chunlong Li, Chao Zhao
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Patent number: 8330228Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.Type: GrantFiled: February 11, 2010Date of Patent: December 11, 2012Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of SciencesInventors: Deyuan Xiao, Xi Wang, Miao Zhang, Jing Chen, Zhongying Xue
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Publication number: 20120306027Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.Type: ApplicationFiled: May 30, 2012Publication date: December 6, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan-Detlef Kronholz, Rohit Pal, Gunda Beernink
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Publication number: 20120299123Abstract: A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Kisik Choi, Vijay Narayanan, Tenko Yamashita, Junli Wang
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Publication number: 20120292719Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Young Way TEH, Michael V. AQUILINO, Arifuzzaman (Arif) SHEIKH, Yun Ling TAN, Hao ZHANG, Deleep R. NAIR, Jinghong H. (John) LI
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Patent number: 8314465Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.Type: GrantFiled: March 3, 2011Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Inc.Inventors: Jong-Ho Lee, Nae-In Lee
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Publication number: 20120286373Abstract: Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value.Type: ApplicationFiled: April 26, 2011Publication date: November 15, 2012Inventors: Huicai Zhong, Zhijiong Luo, Qingqing Liang
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Publication number: 20120286372Abstract: A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.Type: ApplicationFiled: March 19, 2007Publication date: November 15, 2012Inventors: Adrien R. Lavoie, Aaron A. Budrevich, Ashutosh Ashutosh, Huicheng Chang
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Patent number: 8310014Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.Type: GrantFiled: October 27, 2011Date of Patent: November 13, 2012Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior UniversityInventors: David Seo, Jai-kwang Shin, Sun-ae Seo
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Patent number: 8304349Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue.Type: GrantFiled: February 6, 2009Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jr Jung Lin, Yih-Ann Lin, Ryan Chia-Jen Chen
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Patent number: 8304843Abstract: The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness tgd,eff of the gate dielectric is smaller at the source-channel interface than above the channel at a distance from the source-channel interface, the increase in effective gate dielectric thickness tgd,eff being obtained by means of at least changing the physical thickness tgd of the gate dielectriType: GrantFiled: September 8, 2010Date of Patent: November 6, 2012Assignee: IMECInventor: Anne S. Verhulst
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Publication number: 20120273902Abstract: A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Hsien LIN, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
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Publication number: 20120273901Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved.Type: ApplicationFiled: September 27, 2010Publication date: November 1, 2012Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCEInventors: Haizhou Yin, Huicai Zhong, Huilong Zhu, Zhijiong Luo
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Publication number: 20120273903Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.Type: ApplicationFiled: July 12, 2012Publication date: November 1, 2012Applicant: Panasonic CorporationInventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
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Patent number: 8299462Abstract: The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase.Type: GrantFiled: October 25, 2011Date of Patent: October 30, 2012Assignee: Round Rock Research, LLCInventors: Cancheepuram V. Srividya, Noel Rocklein, John Vernon, Jeff Nelson, F. Daniel Gealy, David Korn
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Patent number: 8293610Abstract: By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity.Type: GrantFiled: September 4, 2008Date of Patent: October 23, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Rolf Stephan, Martin Trentzsch, Patrick Press
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Patent number: 8294202Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.Type: GrantFiled: April 6, 2010Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shiu-Ko Jangjian, Szu-An Wu, Sheng-Wen Chen
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Publication number: 20120261770Abstract: A metal gate structure includes a high-K gate dielectric layer, an N-containing layer, a work function metal layer, and an N-trapping layer. The N-containing layer is positioned between the work function metal layer and the high-K gate dielectric layer. The N-trapping layer is positioned between the work function metal layer and the high-K gate dielectric layer, and the N-trapping layer contains no nitrogen or low-concentration nitrogen.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chi-Mao Hsu, Chin-Fu Lin
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Publication number: 20120261769Abstract: A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Inventors: CHEONG M. HONG, BRIAN A. WINSTEAD
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Publication number: 20120261771Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.Type: ApplicationFiled: April 18, 2011Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Reinaldo A. VEGA, Hongwen YAN
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Patent number: 8288802Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.Type: GrantFiled: April 19, 2006Date of Patent: October 16, 2012Assignee: United Microelectronics Corp.Inventors: Po-Lun Cheng, Che-Hung Liu
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Patent number: 8288803Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.Type: GrantFiled: August 31, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Mikael T. Bjoerk, Siegfried F. Karg, Joachim Knoch, Heike E. Riel, Walter H. Riess, Paul M. Solomon
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Patent number: 8288832Abstract: A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.Type: GrantFiled: June 28, 2000Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventor: David L. Chapek
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Patent number: 8288198Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C. with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.Type: GrantFiled: March 12, 2007Date of Patent: October 16, 2012Assignee: Advanced Technology Materials, Inc.Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
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Patent number: 8288767Abstract: A method for forming a thin-film transistor (TFT) includes providing a substrate, forming a first patterned conducting layer on the substrate, forming an organic dielectric layer on the first patterned conducting layer and the substrate, forming a seeding layer on the organic dielectric layer, using the seeding layer as a crystal growing base to form an inorganic semiconductor layer on the seeding layer, and forming a second patterned conducting layer on the inorganic semiconductor layer.Type: GrantFiled: January 4, 2010Date of Patent: October 16, 2012Assignee: National Taiwan UniversityInventors: Ching-Fuh Lin, Chun-Yu Lee
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Publication number: 20120256276Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Publication number: 20120256275Abstract: A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench.Type: ApplicationFiled: April 6, 2011Publication date: October 11, 2012Inventors: Hsin-Fu Huang, Chi-Mao Hsu, Kun-Hsien Lin, Chin-Fu Lin, Tzung-Ying Lee, Min-Chuan Tsai, Yi-Wei Chen, Bin-Siang Tsai, Ted Ming-Lang Guo, Ger-Pin Lin, Yu-Ling Liang, Yen-Ming Chen, Tsai-Yu Wen
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Publication number: 20120256277Abstract: A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.Type: ApplicationFiled: April 11, 2011Publication date: October 11, 2012Inventors: Bruce B. Doris, Kangguo Cheng, Keith Kwong Hon Wong
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Publication number: 20120256278Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.Type: ApplicationFiled: April 5, 2011Publication date: October 11, 2012Applicant: International Business Machines CorporationInventors: Ying Zhang, Qingyun Yang, Hongwen Yan
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Publication number: 20120248550Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Chia-Pin LIN, Sheng-Hsiung WANG, Fan-Yi HSU, Chun-Liang TAI
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Patent number: 8278701Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.Type: GrantFiled: December 17, 2007Date of Patent: October 2, 2012Assignee: NEC CorporationInventor: Masayuki Terai
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Patent number: 8278168Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.Type: GrantFiled: September 20, 2011Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
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Publication number: 20120241873Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Inventor: Wei-Hang Huang
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Patent number: 8274116Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.Type: GrantFiled: November 16, 2009Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Hemanth Jagannathan, Takashi Ando, Vijay Narayanan
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Patent number: 8269281Abstract: Disclosed herein is a method for forming a triple gate oxide of a semiconductor device.Type: GrantFiled: November 16, 2010Date of Patent: September 18, 2012Assignee: Magnachip Semiconductor, Ltd.Inventor: Jung Goo Park
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Patent number: 8269285Abstract: According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an optimal effective work function and enabling low threshold operation to achieve by producing an in-gap level by the addition of a high valence metal in an Hf (or Zr) oxide and changing a position of the in-gap level by nitrogen or fluorine or the like has been realized.Type: GrantFiled: May 2, 2011Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Masato Koyama
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Publication number: 20120228724Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
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Publication number: 20120228723Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Applicant: United Microelectronics Corp.Inventors: Shao-Wei Wang, Gin-Chen Huang, Tsuo-Wen Lu, Chien-Liang Lin, Yu-Ren Wang
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Patent number: 8258586Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: March 11, 2011Date of Patent: September 4, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
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Patent number: 8258588Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.Type: GrantFiled: April 9, 2010Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Jr Jung Lin, Yih-Ann Lin, Jih-Jse Lin, Chao-Cheng Chen, Ryan Chia-Jen Chen, Weng Chang
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Patent number: 8258589Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.Type: GrantFiled: February 9, 2011Date of Patent: September 4, 2012Assignee: Renesas Electronics CorporationInventor: Hiroshi Sunamura
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Patent number: RE43673Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.Type: GrantFiled: September 8, 2006Date of Patent: September 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen