Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
-
Publication number: 20120217591Abstract: A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.Type: ApplicationFiled: December 14, 2011Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventor: Yoichi KAMADA
-
Publication number: 20120217590Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Katherina E. Babich, Alessandro C. Callegari, Christopher D. Sheraw, Eugene J. O'Sullivan
-
Patent number: 8253133Abstract: The present invention provides a method of manufacturing a thin film transistor of a top-contact structure with suppressed deterioration by a process which is easy and suitable for increase in area without damaging an organic semiconductor pattern. The organic semiconductor pattern is formed on a substrate. An electrode material film is formed on the substrate so as to cover the organic semiconductor pattern. A resist pattern is formed on the electrode material film. By wet etching using the resist pattern as a mask, the electrode material film is patterned. By the process, a source electrode and a drain electrode are formed.Type: GrantFiled: July 5, 2011Date of Patent: August 28, 2012Assignee: Sony CorporationInventors: Mao Katsuhara, Nobuhide Yoneya
-
Publication number: 20120211761Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.Type: ApplicationFiled: December 9, 2011Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventor: Atsushi YAMADA
-
Publication number: 20120211844Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.Type: ApplicationFiled: February 10, 2012Publication date: August 23, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Till Schloesser, Peter Baars, Frank Jakubowski
-
Patent number: 8247877Abstract: A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.Type: GrantFiled: August 31, 2009Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey Sleight
-
Patent number: 8232606Abstract: A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.Type: GrantFiled: June 1, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, William K. Henson, Renee T. Mo, Jeffrey Sleight
-
Patent number: 8232611Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.Type: GrantFiled: June 14, 2010Date of Patent: July 31, 2012Assignee: Group IV Semiconductor, Inc.Inventors: Carla Miner, Thomas MacElwee, Marwan Albarghouti
-
Publication number: 20120187506Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: ApplicationFiled: March 28, 2012Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
-
Patent number: 8227874Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.Type: GrantFiled: August 24, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
-
Publication number: 20120181631Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
-
Publication number: 20120181630Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
-
Patent number: 8217472Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.Type: GrantFiled: July 7, 2011Date of Patent: July 10, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Carter, George J. Kluth, Michael J. Hargrove
-
Patent number: 8216907Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: GrantFiled: September 13, 2010Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
-
Publication number: 20120168880Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.Type: ApplicationFiled: March 15, 2012Publication date: July 5, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Hongyong Zhang
-
Patent number: 8212300Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.Type: GrantFiled: August 21, 2009Date of Patent: July 3, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kouichi Nagai
-
Publication number: 20120153405Abstract: In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished.Type: ApplicationFiled: August 2, 2011Publication date: June 21, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Jens Heinrich, Kai Frohberg, Torsten Huisinga, Ronny Pfuetzner
-
Publication number: 20120153406Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate, forming a dipole capping layer over the gate dielectric layer, stacking a metal gate layer and a polysilicon layer over the dipole capping layer, and forming a gate pattern by etching the polysilicon layer, the metal gate layer, the dipole capping layer, and the gate dielectric layer.Type: ApplicationFiled: September 1, 2011Publication date: June 21, 2012Inventors: Woo-Young PARK, Kee-Jeung Lee, Tae-Yoon Kim, Yun-Hyuck Ji
-
Patent number: 8203176Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.Type: GrantFiled: February 4, 2008Date of Patent: June 19, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
-
Publication number: 20120146159Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.Type: ApplicationFiled: November 10, 2011Publication date: June 14, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Cheng WANG, Ming-Chang WEN, Chun-Kuang CHEN, Yao-Ching KU
-
Patent number: 8198184Abstract: An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.Type: GrantFiled: September 30, 2009Date of Patent: June 12, 2012Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Hiroaki Niimi, Luigi Colombo
-
Publication number: 20120139061Abstract: A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.Type: ApplicationFiled: December 2, 2010Publication date: June 7, 2012Applicant: International Business Machines CorporationInventors: Ravikumar Ramachandran, Ying Li, Richard S. Wise
-
Patent number: 8193593Abstract: A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.Type: GrantFiled: November 10, 2009Date of Patent: June 5, 2012Assignee: Intel CorporationInventor: Gang Bai
-
Publication number: 20120133000Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.Type: ApplicationFiled: January 31, 2012Publication date: May 31, 2012Applicant: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
-
Patent number: 8183647Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.Type: GrantFiled: December 11, 2003Date of Patent: May 22, 2012Assignees: Sharp Kabushiki KaishaInventors: Tadahiro Omi, Naoki Ueda
-
Publication number: 20120119308Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.Type: ApplicationFiled: January 18, 2012Publication date: May 17, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Man Fai NG, Rohit Pal
-
Publication number: 20120119307Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ying Li, Henry K. Utomo
-
Patent number: 8174049Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolationType: GrantFiled: December 1, 2009Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Masakazu Goto
-
Publication number: 20120104513Abstract: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Huilong Zhu, Qingqing Liang
-
Patent number: 8169040Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.Type: GrantFiled: June 28, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Masato Koyama, Masahiko Yoshiki
-
Publication number: 20120091540Abstract: In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack.Type: ApplicationFiled: January 5, 2011Publication date: April 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai CHENG, Ka-Hing FUNG, Li-Ping HUANG, Wei-Yuan LU
-
Patent number: 8159028Abstract: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.Type: GrantFiled: August 19, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Jeffrey W. Sleight
-
Patent number: 8159037Abstract: Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer.Type: GrantFiled: August 29, 2008Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-sung Woo, Sun-ae Seo, Dong-chul Kim, Hyun-jong Chung, Dae-young Jeon
-
Patent number: 8154091Abstract: An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric.Type: GrantFiled: April 25, 2008Date of Patent: April 10, 2012Assignees: Centre National de la Recherche Scientifique-CNRS, Institut National Polytechnique de GrenobleInventors: Catherine Dubourdieu, Erwan Yann Rauwel, Vincent Cosnier, Sandrine Lhostis, Daniel-Camille Bensahel
-
Patent number: 8154066Abstract: A dielectric layer containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a titanium aluminum oxide film.Type: GrantFiled: December 1, 2006Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
-
Publication number: 20120080756Abstract: A semiconductor device includes a high dielectric gate insulating film formed on a substrate, and a metal gate electrode formed on the high dielectric gate insulating film. The metal gate electrode includes a crystalline portion and an amorphous portion. A halogen element is eccentrically located in the amorphous portion.Type: ApplicationFiled: December 7, 2011Publication date: April 5, 2012Applicant: PANASONIC CORPORATIONInventors: Jun SUZUKI, Hiroshi Nakagawa
-
Publication number: 20120080760Abstract: The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is disposed on the III-V substrate, and the gate is disposed on the gate dielectric layer, and the gate dielectric layer is praseodymium oxide (PrxOy), which has a high dielectric constant and a high band gap. By using the praseodymium oxide (Pr6O11) as the material of the gate dielectric layer in the present invention, the leakage current could be inhibited, and the equivalent oxide thickness (EOT) of the device with the III-V substrate could be further lowered.Type: ApplicationFiled: December 13, 2010Publication date: April 5, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Edward-Yi Chang, Yueh-Chin Lin
-
Patent number: 8148789Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.Type: GrantFiled: October 29, 2008Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
-
Publication number: 20120074508Abstract: A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.Type: ApplicationFiled: December 1, 2011Publication date: March 29, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenichi OHTSUKA, Naruhisa Miura, Masayuki Imaizumi, Tatsuo Oomori
-
Patent number: 8143616Abstract: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.Type: GrantFiled: April 20, 2009Date of Patent: March 27, 2012Assignees: Oregon State University, Hewlett Packard Development Company, L.P.Inventors: Gregory S. Herman, Peter Mardilovich, Chinmay Betrabet, Chih-hung Chang, Yu-jen Chang, Doo-Hyoung Lee, Mark W. Hoskins
-
Publication number: 20120068275Abstract: A method for fabricating a semiconductor device includes forming a high-dielectric constant insulating film including a high-dielectric constant film; forming a first conductive film including an oxide film on an upper surface thereof and containing at least one of high melting point metal or a compound thereof; forming a second conductive film containing silicon on the first conductive film with the oxide film being interposed therebetween; forming a mixing layer by performing ion implantation to the first and second conductive films to mix a constituent material of the oxide film and silicon of the second conductive film together; and forming the mixing layer into a conductive layer by performing heat treatment.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: PANASONIC CORPORATIONInventor: Tsuyoshi MAKITA
-
Patent number: 8138041Abstract: Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.Type: GrantFiled: June 12, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Troy Graves-Abe, Rashmi Jha, Renee T. Mo, Keith Kwong Hon Wong
-
Publication number: 20120061772Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.Type: ApplicationFiled: September 11, 2010Publication date: March 15, 2012Inventors: Dechao Guo, Keith Kwong Hon Wong
-
Patent number: 8129797Abstract: Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.Type: GrantFiled: June 18, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Herbert L. Ho, Geng Wang
-
Publication number: 20120049171Abstract: Disclosed herein is an electronic device, including: (A) a control electrode; (B) a first electrode and a second electrode; and (C) an active layer composed of an organic semiconductor material layer provided between the first electrode and the second electrode so as to face the control electrode through an insulating layer, wherein a portion of the insulating layer contacting at least the active layer is composed of a layer obtained by curing a material expressed by the general structural formula (1), (2) or (3):Type: ApplicationFiled: August 18, 2011Publication date: March 1, 2012Applicant: SONY CORPORATIONInventors: Toshio Fukuda, Noriyuki Kawashima
-
Publication number: 20120049297Abstract: A gate insulating film includes an oxygen-containing insulating film and a high dielectric constant insulating film formed on the oxygen-containing insulating film and containing a first metal. The high dielectric constant insulating film further includes a second metal different from the first metal. Part of the high dielectric constant insulating film having the maximum composition ratio of the second metal is away from an interface between the high dielectric constant insulating film and the oxygen-containing insulating film and an interface between the high dielectric constant insulating film and the gate electrode. The second metal exists also in a portion of the oxygen-containing insulating film near the interface between the high dielectric constant insulating film and the oxygen-containing insulating film.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Applicant: Panasonic CorporationInventor: Shinji TAKEOKA
-
Publication number: 20120049296Abstract: A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.Type: ApplicationFiled: July 15, 2011Publication date: March 1, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan Kronholz, Markus Lenski, Kerstin Ruttloff, Volker Jaschke
-
Patent number: 8125037Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.Type: GrantFiled: August 12, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
-
Publication number: 20120043622Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.Type: ApplicationFiled: August 17, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eduard A. CARTIER, Qingqing LIANG, Yue LIANG, Yanfeng WANG
-
Publication number: 20120043623Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.Type: ApplicationFiled: August 19, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni