Abstract: The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure.

Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/?5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

Abstract: A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.

Abstract: A bulk & SOI hybrid CMIS device, in which an I/O bulk part and a core logic SOI part are mounted, needs a number of gate stacks to optimize threshold voltage control and causes a problem that the process and structure become complicated. The present invention adjusts the threshold voltage of MISFET at the corresponding part by introducing impurities into any of back gate semiconductor regions, in an SOI semiconductor CMISFET integrated circuit device having a high-k gate insulating film and a metal gate electrode.

Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.

Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.

Abstract: A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.

Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fm portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.

Abstract: A memory cell region comprises a first interlayer insulating film having a bit contact hole, a contact plug formed of a first conductor film embedded in the bit contact hole, and a second conductor film which is stacked on the first interlayer insulating film to constitute a bit line connected to the contact plug. A peripheral transistor region comprises a peripheral transistor having a gate insulating film and a gate electrode stack formed on the gate insulating film. The gate electrode stack is provided with a metal gate film formed on the gate insulating film, an upper gate film stacked on the metal gate film, and a third conductor film stacked on the upper gate film. A height from a semiconductor substrate to a top face of the upper gate film is equal to or lower than a height of a top face of the first interlayer insulating film.

Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

Abstract: A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.

Abstract: A method for producing high-purity lanthanum having a purity of 4N or more excluding rare earth elements other than lanthanum and gas components, wherein lanthanum having a purity of 4N or more is produced by reducing, with distilled calcium, a lanthanum fluoride starting material that has a purity of 4N or more excluding rare earth elements other than lanthanum and gas components, and the obtained lanthanum is subjected to electron beam melting to remove volatile substances. The method for producing high-purity lanthanum, in which Al, Fe, and Cu are respectively contained in the amount of 10 wtppm or less. The method for producing high-purity lanthanum, in which total content of gas components is 1000 wtppm or less. The present invention aims to provide a technique capable of efficiently and stably providing high-purity lanthanum, a sputtering target composed of high-purity lanthanum, and a thin film for metal gate that contains high-purity lanthanum as a main component.

Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.

Abstract: A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.

Abstract: A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.

Abstract: A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

Abstract: A semiconductor device and method for fabricating a semiconductor device are disclosed.

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract: An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.

Abstract: A method for manufacturing a dielectric film having a high dielectric constant is provided. The method is a method for forming, on a substrate, a dielectric film including a metal oxide containing O and elements A and B, wherein the element A comprises Hf or a mixture of Hf and Zr and the element B comprises Al or Si, which includes the steps of: forming a metal oxide having an amorphous structure which has a molar ratio between element A and element B, B/(A+B) of 0.02?(B/(A+B))?0.095 and a molar ratio between element A and O, O/A of 1.0<(O/A)<2.0; and annealing the metal oxide having the amorphous structure at 700° C. or more to form a metal oxide containing a crystal phase with a cubic crystal content of 80% or more.

Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.

Abstract: A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: A hafnium oxide layer, between a III-V semiconductor layer and a metal oxide layer is used to prevent interaction between the III-V semiconductor layer and the metal oxide layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.

Abstract: A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: A gate insulating film includes an oxygen-containing insulating film and a high dielectric constant insulating film formed on the oxygen-containing insulating film and containing a first metal. The high dielectric constant insulating film further includes a second metal different from the first metal. Part of the high dielectric constant insulating film having the maximum composition ratio of the second metal is away from an interface between the high dielectric constant insulating film and the oxygen-containing insulating film and an interface between the high dielectric constant insulating film and the gate electrode. The second metal exists also in a portion of the oxygen-containing insulating film near the interface between the high dielectric constant insulating film and the oxygen-containing insulating film.

Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

Abstract: A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.

Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.

Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.

Abstract: A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

Abstract: A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.

Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

Abstract: Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Abstract: A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode.

Abstract: Provided are a thin film transistor that is capable of suppressing desorption of oxygen and others from an oxide semiconductor layer, and reducing the time to be taken for film formation, and a display device provided therewith. A gate insulation film 22, a channel protection layer 24, and a passivation film 26 are each in the laminate configuration including a first layer 31 made of aluminum oxide, and a second layer 32 made of an insulation material including silicon (Si). The first and second layers 31 and 32 are disposed one on the other so that the first layer 31 comes on the side of an oxide semiconductor layer 23. The oxide semiconductor layer 23 is sandwiched on both sides by the first layers 31 made of aluminum oxide, thereby suppressing desorption of oxygen and others, and stabilizing the electrical characteristics of a TFT 20.

Abstract: In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.

Abstract: When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process.