Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride) Patents (Class 257/411)
  • Publication number: 20120267727
    Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 25, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8294224
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes
  • Publication number: 20120261772
    Abstract: A semiconductor device comprises a gate stack, a source region, a drain region, a contact plug and an interlayer dielectric, the gate stack being formed on a substrate, the source region and the drain region being located on opposite sides of the gate stack and embedded in the substrate, the contact plug being embedded in the interlayer dielectric, wherein the contact plug comprises a first portion which is in contact with the source region and/or drain region, the upper surface of the first portion is flushed with the upper surface of the gate stack, and the angle between a sidewall and a bottom surface of the first portion is less than 90°. There is also provided a method for manufacturing a semiconductor device.
    Type: Application
    Filed: August 9, 2011
    Publication date: October 18, 2012
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8288221
    Abstract: A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takahisa Eimori, Nobuyuki Mise
  • Patent number: 8288803
    Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Siegfried F. Karg, Joachim Knoch, Heike E. Riel, Walter H. Riess, Paul M. Solomon
  • Publication number: 20120256278
    Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicant: International Business Machines Corporation
    Inventors: Ying Zhang, Qingyun Yang, Hongwen Yan
  • Publication number: 20120241875
    Abstract: According to one embodiment, a field-effect transistor comprises a gate insulating film which is provided on a part of a Ge-containing substrate and the gate insulating film includes at least a GeO2 layer, a gate electrode which is provided on the gate insulating film, a source-drain region which is provided in the substrate so as to sandwich a channel region under the gate electrode, and a nitrogen-containing region which is formed on both side parts of the gate insulating film.
    Type: Application
    Filed: September 23, 2011
    Publication date: September 27, 2012
    Inventor: Tsutomu Tezuka
  • Publication number: 20120241874
    Abstract: A method for forming a gate stack of a semiconductor device comprises depositing a gate oxide layer on a channel region of a semiconductor substrate using chemical vapor deposition, atomic layer deposition or molecular layer deposition, depositing a nitride layer on the gate oxide layer, oxidizing the deposited nitride layer, depositing a high-K dielectric layer on the oxidized nitride layer, and forming a metal gate on the high-K dielectric layer.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Inventors: BYUNG-DONG KIM, Ja-Hum Ku
  • Patent number: 8274116
    Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Takashi Ando, Vijay Narayanan
  • Publication number: 20120235237
    Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Man Fai NG, Bin YANG
  • Patent number: 8269281
    Abstract: Disclosed herein is a method for forming a triple gate oxide of a semiconductor device.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 18, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jung Goo Park
  • Patent number: 8269289
    Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 18, 2012
    Assignee: Infineon Technologies AG
    Inventor: Hongfa Luan
  • Patent number: 8264028
    Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: September 11, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Szu Yu Wang
  • Publication number: 20120223398
    Abstract: The present invention relates to a method for manufacturing a contact and a semiconductor device having said contact. The present invention proposes to form first a trench contract of relatively large size, then to form one or more dielectric layer(s) within the trench contact, and then to remove the upper part of the dielectric layer(s) and to fill the same with a conductive material. The use of such a method makes it easy to form a trench contact of relatively large size which is easy for manufacturing; besides, since dielectric layer(s) is/are formed in the trench contact, thence capacitance between a source/drain trench contact and a gate electrode is reduced accordingly.
    Type: Application
    Filed: February 27, 2011
    Publication date: September 6, 2012
    Inventors: Huicai Zhong, Qingqing Liang
  • Publication number: 20120223397
    Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Inventors: Chan-Lon Yang, Chi-Mao Hsu, Chun-Yuan Wu, Tzyy-Ming Cheng, Shih-Fang Tzou, Chin-Fu Lin, Hsin-Fu Huang, Min-Chuan Tsai
  • Patent number: 8258588
    Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Jr Jung Lin, Yih-Ann Lin, Jih-Jse Lin, Chao-Cheng Chen, Ryan Chia-Jen Chen, Weng Chang
  • Patent number: 8258589
    Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Sunamura
  • Patent number: 8258571
    Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: September 4, 2012
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota
  • Patent number: 8258587
    Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuri Masuoka, Shyh-Horng Yang, Peng-Soon Lim
  • Patent number: 8253180
    Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
  • Publication number: 20120205751
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a gate electrode provided on the substrate via a gate insulator. The device further includes a source region of a first conductivity type and a drain region of a second conductivity type provided in the substrate to sandwich the gate electrode, and a channel region provided between the source and drain regions in the substrate. The gate insulator includes a first insulator portion having a first edge which is positioned on the source region and is parallel to a channel-width direction, and a second edge which is positioned on the channel or source region and is parallel to the channel-width direction, and having a first thickness. The gate insulator further includes a second insulator portion positioned on a drain region side with respect to the first insulator portion, and having a second thickness greater than the first thickness.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 16, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya OHGURO
  • Publication number: 20120199919
    Abstract: A gate electrode achieves a desired work function in a semiconductor device including a field-effect transistor equipped with a gate electrode composed of a metal nitride layer. The semiconductor device includes a silicon substrate and a field-effect transistor provided on the silicon substrate and having a gate insulating film and a gate electrode provided on the gate insulating film. The gate insulating film includes a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, and the gate electrode includes at least a metal nitride layer containing Ti and N. At least a part which is in contact with the gate insulating film of the metal nitride layer has a molar ratio between Ti and N (N/Ti ratio) of not less than 1.15 and a film density of not less than 4.7 g/cc.
    Type: Application
    Filed: July 29, 2010
    Publication date: August 9, 2012
    Applicant: CANON ANELVA CORPORATION
    Inventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
  • Patent number: 8237233
    Abstract: In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8237216
    Abstract: Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20120193728
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate insulating film, a silicon-containing second gate insulating film, and a first gate electrode. The first gate insulating film is formed on the semiconductor substrate and made of a material having a dielectric constant higher than a dielectric constant of silicon oxide or silicon oxynitride. The silicon-containing second gate insulating film is formed on the first gate insulating film. The first gate electrode is formed on the silicon-containing second gate insulating film and includes a metal nitride layer. The first gate insulating film, the silicon-containing second gate insulating film and the metal nitride layer form part of the pMOSFET.
    Type: Application
    Filed: January 5, 2012
    Publication date: August 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo MATSUKI
  • Publication number: 20120193716
    Abstract: A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Patent number: 8232605
    Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: July 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan
  • Patent number: 8232611
    Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: July 31, 2012
    Assignee: Group IV Semiconductor, Inc.
    Inventors: Carla Miner, Thomas MacElwee, Marwan Albarghouti
  • Patent number: 8232612
    Abstract: A semiconductor structure. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: James William Adkisson, Michael P. Chudzik, Jeffrey Peter Gambino, Renee T. Mo, Naim Moumen
  • Publication number: 20120187420
    Abstract: An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Andrew H. Simon, Keith Kwong Hon Wong
  • Patent number: 8227874
    Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
  • Publication number: 20120181633
    Abstract: A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5; and a gate insulating film 3 provided between the base 2 and the gate electrode 5. The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2, and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Masayasu Miyata
  • Publication number: 20120181632
    Abstract: A semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A method of manufacturing a semiconductor device including introducing nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 19, 2012
    Applicant: NEC CORPORATION
    Inventors: Heiji WATANABE, Kazuhiko Endo, Kenzo Manabe
  • Patent number: 8217445
    Abstract: A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: July 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hun Jeon, Soo-doo Chae, Ju-hyung Kim, Chung-woo Kim
  • Publication number: 20120168881
    Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
    Type: Application
    Filed: January 27, 2011
    Publication date: July 5, 2012
    Inventors: Haizhou Yin, Huicai Zhong, Huilong Zhu, Zhijiong Luo
  • Patent number: 8212300
    Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: July 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Publication number: 20120161251
    Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Michael G. Haverty, Sadasivan Shankar
  • Patent number: 8207584
    Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 26, 2012
    Assignees: Renesas Electronics Corporation, Rohm Co., Ltd.
    Inventors: Toshihide Nabatame, Kunihiko Iwamoto, Yuuichi Kamimuta
  • Publication number: 20120153373
    Abstract: A gate structure is described, including a dielectric layer, a gate conductive layer and a stacked cap structure. The dielectric layer is disposed between a substrate and the gate conductive layer. The gate conductive layer is disposed between the dielectric layer and the stacked cap structure. The stacked cap structure disposed on the gate conductive layer includes at least two insulating layers having different materials and contacting each other.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Jyun-Huan Chen
  • Publication number: 20120153400
    Abstract: A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Wei Tian, Venugopalan Vaithyanathan, Cedric Bedoya, Markus Siegert
  • Patent number: 8203188
    Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: June 19, 2012
    Assignee: Broadcom Corporation
    Inventor: Akiro Ito
  • Patent number: 8198184
    Abstract: An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 12, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi, Luigi Colombo
  • Publication number: 20120139062
    Abstract: A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jun Yuan, Dechao Guo, Keith Kwong Hon Wong, Yanfeng Wang, Gan Wang
  • Patent number: 8193593
    Abstract: A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventor: Gang Bai
  • Patent number: 8193586
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
  • Patent number: 8193032
    Abstract: A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Zhihong Chen, Dechao Guo, Shu-jen Han, Kai Zhao
  • Patent number: 8188547
    Abstract: A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Manabe, Toshihiro Iizuka, Daisuke Ikeno
  • Patent number: 8183647
    Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 22, 2012
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Tadahiro Omi, Naoki Ueda
  • Publication number: 20120119309
    Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 17, 2012
    Inventor: Katsuyuki HORITA
  • Patent number: 8178934
    Abstract: The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015?(B/(A+B+N))?0.095 and N/(A+B+N) has a range of 0.045?(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0<(O/A)<2.0, and having a noncrystalline structure; and a step of performing an annealing treatment at 700° C. or higher on the metallic oxynitride having a noncrystalline structure to form a metallic oxynitride including a crystalline phase with a cubical crystal incorporation percentage of 80% or higher.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: May 15, 2012
    Assignee: Canon Anelva Corporation
    Inventors: Naomu Kitano, Takashi Nakagawa, Toru Tatsumi