Abstract: A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.

Abstract: A semiconductor device may include a semiconductor substrate, a diffusion layer provided over the semiconductor substrate, source and drain diffusion regions provided in upper regions of the diffusion layer, a gate insulating film provided over the source and drain diffusion regions and the diffusion layer, a gate electrode provided on the gate insulating film and positioned over the diffusion layer, a passivation film provided over the gate insulating film and the gate electrode, an insulating film that covers the passivation film, and contact plugs that penetrate the insulating film, the passivation film, and the gate insulating film, so that the contact plugs reach the source and drain diffusion regions. The contact plugs are positioned near side walls of the gate electrode. Fluorine is implanted to the passivation film. Fluorine is diffused to a silicon-insulator interface between the gate insulating film and the diffusion layer under the gate electrode.

Abstract: A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.

Abstract: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

Abstract: The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of <2.24 eV electron temperature, so that the generation of ions tending to damage any insulating film is reduced to thereby realize high-quality oxynitriding. Further, there is provided a process for producing an electronic appliance in which use is made of the method of plasma treatment.

Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.

Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.

Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.

Abstract: A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and crystalline phases lines with a high dielectric constant, which are dispersed in the amorphous matrix layer. The semiconductor device further includes a gate electrode that is provided on the gate insulation film.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.

Abstract: A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.

Abstract: Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has a channel formation region defined between two source and drain regions formed on a semiconductor substrate a bottom insulating film, a charge storage film and a top insulating film formed in order at least on the channel formation region, the charge storage film having a charge storage function, and a gate electrode formed on the top insulating film. The bottom insulating film is formed from a plurality of films containing nitrogen such that the content of nitrogen of a lowermost one of the films which contacts with the channel formation region and an uppermost one of the films which contacts with the gate electrode is higher than that of the other one or ones of the films which exist between the uppermost and lowermost films.

Abstract: Methods and apparatus are provided for fabricating a transistor. The transistor comprises a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and an oxygen-gettering conductive layer overlying the high-k dielectric layer. The oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive layer.

Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.

Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.

Abstract: Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: A method for manufacturing a semiconductor device comprises preparing a base; forming a silicon oxide film including hydrogen or deuterium on the base; diffusing nitrogen into the silicon oxide film to form a gate insulating film; forming a gate electrode on the gate insulating film; ion doping the base to form source and drain regions along side a channel region; and forming a source electrode connected to the source region and a drain electrode connected to the drain region, the gate insulating film having a region where B/A is in the range of 1.6 to 10, where A is a concentration of nitrogen, and B is a concentration of hydrogen or deuterium, and the region is Y/10 of the thickness of the gate insulating film from the interface between the gate insulating film and the base, where Y is an average thickness of the gate insulating film.

Abstract: Substrate devices having tuned work functions and methods of forming thereof are provided. In some embodiments, forming devices on substrates may include depositing a dielectric layer atop a substrate having a conductivity well; depositing a work function layer comprising titanium aluminum or titanium aluminum nitride having a first nitrogen composition atop the dielectric layer; etching the work function layer to selectively remove at least a portion of the work function layer from atop the dielectric layer; depositing a layer comprising titanium aluminum or titanium aluminum nitride having a second nitrogen composition atop the work function layer and the substrate, wherein at least one of the work function layer or the layer comprises nitrogen; etching the layer and the dielectric layer to selectively remove a portion of the layer and the dielectric layer from atop the substrate; and annealing the substrate at a temperature less than about 1500 degrees Celsius.

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.

Abstract: A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed to etch the second silicon oxide layer. After that, a wet etching is performed to etch the silicon nitride layer and the first silicon oxide layer. The aforesaid wet etching is performed by utilizing an RCA cleaning solution. Furthermore, the silicon nitride layer is formed by the SINGEN process. Therefore, the first and second silicon oxide layer and the silicon nitride layer can be etched together by the RCA cleaning solution.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.

Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

Abstract: A thin film transistor having an improved gate dielectric layer is disclosed. The gate dielectric layer comprises a poly(hydroxyalkyl acrylate-co-acrylonitrile) based polymer. The resulting gate dielectric layer has a high dielectric constant and can be crosslinked. Higher gate dielectric layer thicknesses can be used to prevent current leakage while still having a large capacitance for low operating voltages. Methods for producing such gate dielectric layers and/or thin film transistors comprising the same are also disclosed.

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract: A method of manufacturing a semiconductor device includes: forming a gate insulating film over a semiconductor substrate; forming a mask that has an opening at a position corresponding to the gate insulating film formed in an NMOSFET forming region and covers the gate insulating film; forming a first metal layer over the gate insulating film disposed in the NMOSFET forming region and the mask formed in a PMOSFET forming region; and performing a heat treatment to thermally diffuse a metal material forming the first metal layer into the gate insulating film formed in the NMOSFET forming region.

Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.

Abstract: There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted MOS transistor including a first gate electrode comprising at least one type of crystalline phase selected from the group consisting of a WSi2 crystalline phase, an MoSi2 crystalline phase, an NiSi crystalline phase, and an NiSi2 crystalline phase as silicide region (1). The nMOS transistor is a fully depleted MOS transistor comprising at least one type of crystalline phase selected from the group consisting of a PtSi crystalline phase, a Pt2Si crystalline phase, an IrSi crystalline phase, an Ni2Si crystalline phase, and an Ni3Si crystalline phase as silicide region (2).

Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

Abstract: A field-effect transistor having a high-quality semiconductor/oxide interface and a method of fabricating the field-effect transistor are provided. The field-effect transistor includes a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a semiconductor layer formed in the donor layer and containing Pt; an oxide layer formed on the semiconductor layer and containing a perovskite-type oxide which functions as a gate insulating film; and a gate electrode formed on the oxide layer.

Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

Abstract: A display substrate includes a substrate, a first insulating layer, an undercut compensating member, a first electrode, a second insulating layer and a first conductive pattern. The first insulating layer is formed on the substrate. The undercut compensating member is formed on the first insulating layer. The undercut compensating member has an etching rate smaller than that of the first insulating layer. The first electrode is formed on a portion of the undercut compensating member. The second insulating layer is formed on the first insulating layer. The second insulating layer has a contact hole through which a portion of the first electrode and a remaining portion of the undercut compensating member. The first conductive pattern electrically connected to the first electrode through the contact hole.

Abstract: A flash memory device includes a tunnel insulating layer formed over a semiconductor substrate, a charge trap layer formed over the tunnel insulating layer and configured to trap electric charges, a blocking insulating layer formed over the charge trap layer, and a gate electrode formed over the blocking insulating layer and including a first conductive layer and a second conductive layer doped with N and P impurities respectively. Further, a method of erasing a flash memory device includes providing a flash memory device including a gate electrode having a first conductive layer and a second conductive layer doped with N and P impurities respectively, and performing an erase operation in a state where a thickness of a depletion layer at an interface of a PN junction comprising the first conductive layer and the second conductive layer is increased due to a negative potential bias applied to the gate electrode.

Abstract: In a p-channel-type field-effect transistor having a metal gate electrode, a technique capable of stably obtaining a desired threshold voltage is provided. On a gate insulating film composed of a HfSiON film and formed on a semiconductor substrate, there is formed a metal gate electrode partially having a conductive film with a Me1-xAlxOy (0.2?x?0.75, 0.2?y?1.5) composition having a Me-O—Al—O-Me bond or a metal gate electrode partially having a conductive film with a Me1-xAlxN1-zOz (0.2?x?0.75, 0.1?z?0.9) composition having a Me-O—Al—N-Me bond.

Abstract: A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor layer, and a gate insulating layer for insulating the source electrode and the drain electrode from the gate electrode, wherein the gate insulating layer includes composite particles in which a hydrophobic compound is provided on the surfaces of insulating inorganic particles.

Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.