Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract: A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

Abstract: A method for manufacturing a semiconductor device comprises preparing a base; forming a silicon oxide film including hydrogen or deuterium on the base; diffusing nitrogen into the silicon oxide film to form a gate insulating film; forming a gate electrode on the gate insulating film; ion doping the base to form source and drain regions along side a channel region; and forming a source electrode connected to the source region and a drain electrode connected to the drain region, the gate insulating film having a region where B/A is in the range of 1.6 to 10, where A is a concentration of nitrogen, and B is a concentration of hydrogen or deuterium, and the region is Y/10 of the thickness of the gate insulating film from the interface between the gate insulating film and the base, where Y is an average thickness of the gate insulating film.

Abstract: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen.

Abstract: The present invention relates to a mixed metal oxide of formula SrM1-xTixO3 wherein x is 0>x>1 and M is Hf or Zr, such as a strontium-hafnium-titanium oxide orstrontium-zirconium-titanium oxide, and to a functional device comprising the mixed metal oxide.

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Abstract: An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric.

Abstract: Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.

Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: A semiconductor device includes a plurality of gate insulating films formed on a semiconductor substrate. Of the plurality of gate insulating films, the gate insulating film having a smallest thickness in an HP transistor formation region is a silicon oxide film, and each of the remaining gate insulating films in an I/O transistor formation region and an LP transistor formation region is a silicon oxynitride film.

Abstract: A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric layer containing a HfO2/ZrO2 nanolaminate may be realized in a wide variety of electronic devices and systems.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M?Oy) or amorphous metal oxynitride (M?OyNz).

Abstract: A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ? the N concentration in a bulk of the annealed N-enhanced SiON gate layer ?2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.

Abstract: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.

Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract: There are provided a MOSFET structure and a method for fabricating the same. The MOSFET structure comprises: a semiconductor substrate; a gate stack formed on the semiconductor substrate, including a high-k gate dielectric layer and a gate conductor layer formed sequentially on the semiconductor substrate; a first spacer which surrounds at least the high-k gate dielectric layer and comprises a La containing oxide; and a second spacer which surrounds the gate stack and the first spacer and is higher than the first spacer. Embodiments of the present invention are applicable to the fabrication of integrated circuits.

Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.

Abstract: A transistor is formed in the active region of a semiconductor substrate. A sidewall structure is disposed on the sidewalls of a gate electrode. A stress control film covers the semiconductor substrate. The sidewall structure includes a first portion extending along partial upper sidewalls of the gate electrode, a second portion extending from partial lower sidewalls of the gate electrode to partial surfaces of the active region, a third portion extending along partial surfaces of the first active region outer than the second portions, and a fourth portion facing the sidewalls of the gate electrode and an upper surface of the active region via the first to third portions. A Young's modulus of the first portion is lower than that of the third portion. The transistor is of an n-type and stress in the stress control film is tensile, or the transistor is of a p-type and stress is compressive.

Abstract: The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the layer provides the functionality of a thinner silicon dioxide layer, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Abstract: A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.

Abstract: A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor including an oxide semiconductor film, the oxide semiconductor film is subjected to dehydration or dehydrogenation performed by heat treatment. In addition, as a gate insulating film in contact with the oxide semiconductor film, an insulating film containing oxygen, preferably, a gate insulating film including a region containing oxygen with a higher proportion than the stoichiometric composition is used. Thus, oxygen is supplied from the gate insulating film to the oxide semiconductor film. Further, a metal oxide film is used as part of the gate insulating film, whereby reincorporation of an impurity such as hydrogen or water into the oxide semiconductor is suppressed.

Abstract: A method for fabricating a sol-gel film composition for use in a thin film transistor is disclosed. The method includes fabricating the sol-gel dielectric composition by solution processing at a temperature in the range 60° C. to 225° C. The sol-gel film made by the method, and an organic thin-film transistor incorporating the sol-gel film are also disclosed.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.

Abstract: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

Abstract: A semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by favorable nitrogen concentration profile of a gate insulating film, and a method for manufacturing the semiconductor device. The semiconductor device fabricating method operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, including introducing an oxynitriding species previously diluted by plasma excitation gas into a plasma processing apparatus, generating an oxynitriding species by a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.

Abstract: One object is to provide a semiconductor element in which leakage current between a gate electrode and a channel formation region is suppressed even when the gate electrode is miniaturized as a result of miniaturization of the semiconductor element. Another object is to provide a downsized and high-performance semiconductor device. A semiconductor element having the following structure is manufactured: an insulating film containing gallium oxide and having a relative permittivity of 10 or more is formed as a gate insulating film over a semiconductor layer having a function of a channel formation region; and a gate electrode is formed over the gallium oxide. Further, a semiconductor device is manufactured by using the semiconductor element.

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract: Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom.

Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVA) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVB); and M?xOy, where M? is a second metal species selected from the group 3 (IIIB) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.

Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

Abstract: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.

Abstract: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric constant insulating film are formed sequentially in this order on one surface of a silicon substrate.

Abstract: A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x?0, 1?y?0, z?0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.