Magnetic Field Patents (Class 257/421)
  • Patent number: 10665676
    Abstract: Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 26, 2020
    Assignee: Intersil Americas LLC
    Inventors: Dev Alok Girdhar, Jeffrey Michael Johnston
  • Patent number: 10658577
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Iwata
  • Patent number: 10650873
    Abstract: A memory array that comprises three dimensionally stacked two-dimensional memory arrays. The memory array includes a first layer and a second layer oriented orthogonal to the first layer. The memory array further includes a magnetic tunnel junction adjacent to each of the first layer and the second layer. The magnetic tunnel junction further includes a first magnetic layer adjacent to the second layer. Additionally, the magnetic tunnel junction includes a second magnetic layer adjacent to the first layer. The magnetic tunnel junction also includes a tunnel layer adjacent to the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Carnegie Mellon University
    Inventors: Jian-Gang Zhu, Chia-Ling Chien, Qinli Ma
  • Patent number: 10651370
    Abstract: A magnetic data recording element for magnetic random access memory data recording. The magnetic data recording element includes a magnetic tunnel junction element that includes a magnetic reference layer, a magnetic free layer and a non-magnetic barrier layer located between the non-magnetic reference layer and the magnetic free layer. The magnetic free layer includes a layer of Hf that causes the magnetic free layer to have an increased perpendicular magnetic anisotropy. This increased perpendicular magnetic anisotropy improves data retention and increases thermal stability, by preventing the magnetization of the magnetic free layer from inadvertently losing its magnetic orientation.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz, Jorge Vasquez, Thomas D. Boone
  • Patent number: 10643680
    Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Pinarbasi, Bartek Kardasz
  • Patent number: 10643643
    Abstract: Embodiments of the present disclosure generally relate to a spin torque oscillator device (STO) including a high damping field generation layer or a damping enhancing capping layer for use in microwave assisted magnetic recording (MAMR) write heads. In one embodiment, a STO device for a MAMR write head includes a spin polarization layer, a spacer layer over the spin polarization layer, and a field generation layer over the spacer layer. The field generation layer has a damping in a range from about 0.5% to about 20%.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zheng Gao, James Mac Freitag, Susumu Okamura
  • Patent number: 10636962
    Abstract: Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Sungryul Kim, Seung Hyuk Kang
  • Patent number: 10636794
    Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Patent number: 10634634
    Abstract: Disclosed is a microsensor package. Particularly, disclosed is a microsensor package, in which a sensing chip is packaged by using PCBs stacked on top of one another, whereby the thickness of the package slim can be kept slim, and at the same time, it can be manufactured at a low cost and can be easily manufactured.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 28, 2020
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10629231
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 21, 2020
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10629650
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Patent number: 10622545
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru Toko, Keiji Hosotani, Hisanori Aikawa, Tatsuya Kishi
  • Patent number: 10608046
    Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Patent number: 10608174
    Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Wei-Chuan Chen
  • Patent number: 10601368
    Abstract: A spin torque oscillation generator includes a spin reference layer and a spin oscillation layer. The spin reference layer has a first magnetization direction. The spin reference layer is configured to receive a current and generate a spin-polarized current. The spin oscillation layer has a second magnetization direction. The second magnetization direction is different than the first magnetization direction. The spin oscillation layer is configured to receive the spin-polarized current from the spin reference layer. The spin-polarized current generates a spin torque based on the second magnetization direction of the spin oscillation layer. The spin torque generates a spin torque output signal.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: March 24, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Bin Lu
  • Patent number: 10600956
    Abstract: An electronic device is provided to include a semiconductor memory which includes one or more variable resistance elements, wherein each variable resistance element may include a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; and a sidewall spacer disposed on a sidewall of the variable resistance element and including an amorphous silicon.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Ga-Young Ha
  • Patent number: 10600955
    Abstract: According to an embodiment, a semiconductor storage device includes a substrate. A stack is provided above the substrate, and includes a resistance change element and a metal layer provided above the resistance change element. A first insulating layer is provided on a side surface of the stack. A second insulating layer is provided on the first insulating layer. And an electrode is provided on the metal layer and on the first insulating layer so as to extend along a stacking direction in the second insulating layer. A lower surface of the electrode as viewed in the direction has a diameter greater than a diameter of an upper surface of the stack as viewed in the direction. A lowermost portion of the electrode is at a same level as an uppermost portion of the metal layer as viewed in the direction.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuyuki Sonoda
  • Patent number: 10586580
    Abstract: A magnetic tunnel junction element with a high tunnel magnetic resistance ratio can prevent a recording layer from being damaged. A reference layer includes a ferromagnetic body, and has magnetization direction fixed in the vertical direction. A barrier layer includes non-magnetic body, and disposed on one surface side of the reference layer. A recording layer is disposed to sandwich barrier layer between itself and reference layer. The recording layer includes a first ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in a vertical direction; a first non-magnetic layer including at least one of Mg, MgO, C, Li, Al, and Si, second non-magnetic layer including at least one of Ta, Hf, W, Mo, Nb, Zr, Y, Sc, Ti, V, and Cr, and second ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in a vertical direction.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 10, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Tetsuo Endoh, Hideo Ohno
  • Patent number: 10586917
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 10, 2020
    Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Patent number: 10586914
    Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 10, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Sajjad Amin Hassan, Mahendra Pakala, Jaesoo Ahn
  • Patent number: 10586919
    Abstract: A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 10, 2020
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
  • Patent number: 10580968
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan
  • Patent number: 10580965
    Abstract: A plurality of magnetic tunnel junction structures is arranged in rows and columns on a substrate. A plurality of top electrodes is disposed on the plurality of magnetic tunnel junction structures, respectively. A plurality of bit lines is disposed on the substrate. One of the plurality of bit lines is disposed between two magnetic tunnel junction structures, adjacent to each other, of the plurality of magnetic tunnel junction structures. A top surface of each of the plurality of bit lines is disposed at substantially the same level as a top surface of each of the plurality of top electrodes.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Junghoon Bak
  • Patent number: 10578683
    Abstract: A magnetic sensor circuit includes a first magnetic detection portion and a second magnetic detection portion. The first magnetic detection portion has: output terminals for signals corresponding to strength of a magnetic field in a first direction; a positive terminal to which a drive current of the signals is supplied; and a negative terminal from which the drive current flows out. The second magnetic detection portion has: output terminals for signals corresponding to strength of a magnetic field in a second direction; and a positive terminal to which the drive current of the signals is supplied. The positive terminal of the first magnetic detection portion, the negative terminal of the first magnetic detection portion, and the positive terminal of the second magnetic detection portion are connected in series with respect to a path of the drive current of the first signals supplied from a power supply.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 3, 2020
    Assignee: ABLIC INC.
    Inventor: Masao Iriguchi
  • Patent number: 10580452
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are executable by a controller to cause the controller to: detect, by the controller, a change in a resistance value of at least one of a plurality of detector structures, for identifying a defect on a magnetic medium. Each of the detector structures includes a pair of conductive layers separated by an insulating material. Moreover, none of the detector structures include an operable reader for reading data from a magnetic medium. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Edwin R. Childers, Jason Liang
  • Patent number: 10580905
    Abstract: The present disclosure provides a thin film transistor and a method of preparing the same. The thin film transistor includes a substrate; a gate provided on the substrate; a gate insulating layer provided on the substrate and completely covering the gate; a semiconductor layer provided on the gate insulating layer; and an etch stop layer and a source/drain electrode layer provided on the semiconductor layer. The etch stop layer includes a first stop layer provided on a side of the channel region, the side being away from the gate, and a second stop layer provided on the first stop layer. The thin film transistor and the method for preparing the same as proposed in the present disclosure can prevent the device from being damaged by a high temperature and reduce the film-forming time and increase productivity; the SiO2 can be prepared at a lower temperature.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 3, 2020
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Zhiwu Wang
  • Patent number: 10573688
    Abstract: The disclosed technology generally relates to magnetic devices, and more particular to a magnetic structure, and a magnetic tunnel junction device and a magnetic random access memory including the magnetic structure. According to an aspect, a magnetic structure for a magnetic tunnel junction (MTJ) device includes a free layer, a tunnel barrier layer, a reference layer, a hard magnetic layer, and an inter-layer stack arranged between the hard magnetic layer and the reference layer. The inter-layer stack includes a first ferromagnetic sub-layer, a second ferromagnetic sub-layer and a non-magnetic spacer sub-layer. The non-magnetic spacer sub-layer is arranged in contact with and between the first ferromagnetic sub-layer and the second ferromagnetic sub-layer and is adapted to provide a ferromagnetic coupling of a magnetization of the first ferromagnetic sub-layer and a magnetization of the second ferromagnetic sub-layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 25, 2020
    Assignee: IMEC vzw
    Inventor: Johan Swerts
  • Patent number: 10573805
    Abstract: According to one embodiment, a magnetic memory device includes a conductive underlayer having an amorphous structure and containing at least one first predetermined element selected from molybdenum (Mo), magnesium (Mg), rhenium (Re), tungsten (W), vanadium (V), and manganese (Mn), and a stacked structure provided on the underlayer, and including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akiyuki Murayama, Takeshi Iwasaki, Tadashi Kai, Tadaomi Daibou, Masaki Endo, Taichi Igarashi, Junichi Ito
  • Patent number: 10566385
    Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kyu Lee, Gwan-hyeob Koh, Hong-kook Min
  • Patent number: 10566041
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10566384
    Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
  • Patent number: 10559751
    Abstract: A conductive microstud is formed in a recess of an insulator layer formed on the substrate. A bottom pedestal is formed on a top surface of the microstud. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A top pedestal is formed on a top surface of the bottom pedestal. The top surface of at least one of the bottom pedestal and top pedestal is planarized. A conductive layer is formed on a top surface of the top pedestal. Next, a conical structure is formed. The conical structure is comprised of at least the conductive layer and a top portion of the top pedestal.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert, Daniel C Edelstein
  • Patent number: 10553299
    Abstract: A magnetic domain wall type analog memory element includes: a magnetization fixed layer in which magnetization is oriented in a first direction; a non-magnetic layer provided in one surface of the magnetization fixed layer; a magnetic domain wall drive layer including a first area in which magnetization is oriented in the first direction, a second area in which magnetization is oriented in a second direction opposite to the first direction, and a magnetic domain wall formed as an interface between the areas and provided to sandwich the non-magnetic layer with respect to the magnetization fixed layer; and a current controller configured to cause a current to flow between the magnetization fixed layer and the second area at the time of reading.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 4, 2020
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10553781
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10553785
    Abstract: This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10541014
    Abstract: Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Elijah V. Karpov, Kaan Oguz, Kevin P. O'Brien, Charles C. Kuo, Mark L. Doczy, Uday Shah, Yih Wang
  • Patent number: 10541362
    Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 21, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
  • Patent number: 10539631
    Abstract: A charge-carrier Hall-effect sensor comprising: a semiconductor or a semimetal layer; a pair of electric current contacts in electrical contact with the semiconductor or semimetal layer and separated in a first longitudinal direction along a first electric current channel; a pair of voltage contacts in electrical contact with the semiconductor or semimetal layer and separated in a second transverse direction, orthogonal to the first direction, and positioned on either side of the electric current channel; an electrically insulating layer underlying the semiconductor or the semimetal layer; and a ferromagnetic layer underlying the electrically insulating layer comprising at least one region having a magnetic moment with a component perpendicular to a plane comprising the pair of electric current contacts and the pair of voltage contacts.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 21, 2020
    Assignee: Nokia Technologies Oy
    Inventor: Matteo Bruna
  • Patent number: 10529916
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10529913
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell disposed on a substrate, the MRAM cell comprises a magnetic tunnel junction (MTJ) disposed between a lower electrode and an upper electrode. A sidewall spacer arranged along opposite sidewalls of the MRAM cell. An upper interconnect wire directly contacting an upper surface of the upper electrode along an interface continuously extending from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Patent number: 10529920
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Hung-Chan Lin, Yu-Ping Wang, Yu-Chun Chen, Chiu-Jung Chiu
  • Patent number: 10522752
    Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a boron containing free layer (FL) is subjected to a plasma treatment with inert gas, and a natural oxidation (NOX) process to form B2O3 before overlying layers are deposited. A metal layer such as Mg is deposited on the FL as a first step in forming a Hk enhancing layer that increases FL perpendicular magnetic anisotropy, or as a first step in forming a tunnel barrier layer on the FL. One or more anneal steps are essential in assisting B2O3 segregation from the free layer and thereby increasing the FL magnetic moment. A post-oxidation plasma treatment may also be used to partially remove B2O3 proximate to the FL top surface before the metal layer is deposited. Both plasma treatments use low power (<50. Watts) to remove a maximum of 2. Angstroms FL thickness.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
  • Patent number: 10522746
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Patent number: 10520559
    Abstract: Hall effect elements are driven by current generators that use vertical epi resistors disposed away from an edge of a substrate upon which, within which, or over which, the Hall effect elements, the current generators, and the vertical epi resistors are disposed.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 31, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Juan Manuel Cesaretti, Andreas P. Friedrich, Gerardo A. Monreal, Alejandro Gabriel Milesi
  • Patent number: 10522741
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10522748
    Abstract: The present invention relates to a magnetic device including a spin-current pattern generating a spin current perpendicular to a main plane of the spin-current pattern by an in-plane current, and a free magnetic layer disposed in contact with the spin-current pattern and having a perpendicular magnetic anisotropy magnetically switchable by the spin current.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 31, 2019
    Assignee: UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITY
    Inventor: Jongill Hong
  • Patent number: 10522747
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACUTING COMPANY, LTD.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10522753
    Abstract: A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10515996
    Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Witold Kula, Wayne I. Kinney, Gurtej S. Sandhu
  • Patent number: 10510950
    Abstract: A magnetoresistive memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer, a magnetization direction of the second magnetic layer being invariable, a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer. The first magnetic layer has a stacked layer structure in which an amorphous magnetic material layer is sandwiched between crystalline magnetic material layers. The magnetoresistive memory device further includes nonmagnetic material layers provided between one of the crystalline magnetic material layers and the amorphous magnetic material layer, and between the other crystalline magnetic layer and the amorphous magnetic material layer, respectively.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: December 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Watanabe, Toshihiko Nagase, Youngmin Eeh, Kazuya Sawada, Makoto Nagamine, Tadaaki Oikawa, Kenichi Yoshino, Hiroyuki Ohtori