Magnetic Field Patents (Class 257/421)
  • Patent number: 10319902
    Abstract: Some embodiments are directed to a magnetoresistive device, including a free layer having an easy magnetization direction in a perpendicular direction or in an in-plane direction; a fixed layer having the easy magnetization direction which is in the perpendicular direction when the easy magnetization direction of the free layer is in the perpendicular direction or in the in-plane direction when the easy magnetization direction of the free layer is in the in-plane direction; and a non-magnetic layer disposed between the free layer and the fixed layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 11, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Rie Matsumoto, Hiroko Arai, Shinji Yuasa, Hiroshi Imamura
  • Patent number: 10305025
    Abstract: A magnetic memory device including a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction; a second magnetic layer having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the first magnetization direction, and having a top surface including a recess portion or a bottom surface including a recess portion; a third magnetic layer provided between the first magnetic layer and the second magnetic layer, and having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the second magnetization direction; and a nonmagnetic layer provided between the first magnetic layer and the third magnetic layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jyunichi Ozeki, Hiroyuki Ohtori, Kuniaki Sugiura, Yutaka Hashimoto, Katsuya Nishiyama
  • Patent number: 10302711
    Abstract: An article may include a substantially perpendicularly magnetized free layer having a first magnetic orientation in the absence of an applied magnetic field. The article may also include a spin Hall channel layer configured to conduct a spin current configured to subject the perpendicularly magnetized free layer to a magnetic switching torque and a substantially in-plane magnetized bias layer configured to bias the substantially perpendicularly magnetized free layer to a second magnetic orientation. The second magnetic orientation is different than the first magnetic orientation and is out of a plane of the substantially perpendicularly magnetized free layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 28, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Jian-Ping Wang, Angeline Klemm Smith, Mahdi Jamali, Zhengyang Zhao
  • Patent number: 10304508
    Abstract: A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 28, 2019
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Satoshi Sugahara, Yota Takamura, Shigeki Nakagawa
  • Patent number: 10305027
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 28, 2019
    Assignees: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi Kato, Tadaomi Daibou, Yuuzo Kamiguchi, Naoharu Shimomura, Junichi Ito, Hiroaki Sukegawa, Mohamed Belmoubarik, Po-Han Cheng, Seiji Mitani, Tadakatsu Ohkubo, Kazuhiro Hono
  • Patent number: 10297896
    Abstract: The invention relates to a three-dimensional LC electrical resonator device having a given resonant frequency of 100 gigahertz or more, comprising: a separating layer; a first track made of a conductor and comprising two overlapping portions; and a second track made of a conductor, the second track comprising two overlapping portions and an inductive loop connecting the two overlapping portions, the first track and the second track respectively being formed on either side of the separating layer, each overlapping portion of the first track being placed facing a respective overlapping portion of the second track so as to form two capacitors that are spatially spaced apart from each other.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 21, 2019
    Assignees: Universite Paris Diderot Paris 7, Centre National de la Recherche Scientifique (CNRS)
    Inventors: Pascal Desfonds, Yanko Todorov, Carlo Sirtori
  • Patent number: 10297747
    Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 21, 2019
    Assignee: Everpsin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
  • Patent number: 10297301
    Abstract: A magnetic device and method for providing the magnetic device junction are described. The magnetic device includes magnetic junctions and spin-orbit interaction (SO) active layer(s). The magnetic junction includes a pinned layer, a perpendicular enhancement layer (PEL), an insertion layer between the pinned layer and PEL, a free layer and a nonmagnetic spacer layer between the PEL and free layer. The insertion layer includes at least one magnetic material and at least one high crystallization temperature nonmagnetic material. The PEL is between the insertion layer and the nonmagnetic spacer layer. The free layer is switchable between a plurality of stable magnetic states. The PEL and free and pinned layers each has a perpendicular magnetic anisotropy energy greater than its out-of-plane demagnetization energy. The SO active layer(s) are adjacent to the free layer, carry a current in-plane and exert a SO torque on the free layer due to the current.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Don Koun Lee, Mohamad Towfik Krounbi
  • Patent number: 10297746
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 10276633
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Patent number: 10276226
    Abstract: A method for measuring a temperature of magnetic junction switchable using spin transfer. The magnetic junction includes at least one magnetic layer. The method includes measuring a temperature variation of at least one magnetic characteristic for the magnetic layer(s) versus temperature. The method also includes measuring a bias variation in the magnetic characteristic versus an electrical bias for the magnetic junction. This measurement is performed such that spin transfer torque-induced variation(s) in the magnetic characteristic(s) are accounted for. The temperature versus the electrical bias for the magnetic junction is determined based on the temperature variation and the bias variation.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sebastian Schafer, Dmytro Apalkov, Alexey Vasilyevitch Khvalkovskiy, Vladimir Nikitin, Robert Beach, Zheng Duan
  • Patent number: 10276225
    Abstract: A magnetic device and method for providing the magnetic device are described. The magnetic device includes magnetic junctions and spin-orbit interaction (SO) active layer(s). Each magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than an out-of-plane demagnetization energy. The pinned layer includes a magnetic barrier layer between a magnetic layer and a high PMA layer including at least one nonmagnetic component. The magnetic barrier layer includes Co and at least one of Ta, W and Mo. The magnetic barrier layer is for blocking diffusion of the nonmagnetic component. The SO active layer(s) are adjacent to the free layer. The SO active layer(s) carry a current in-plane and exert a SO torque on the free layer due to the current. The free layer is switchable between stable magnetic states using the SO torque.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Dmytro Apalkov, Gen Feng, Mohamad Towfik Krounbi
  • Patent number: 10269727
    Abstract: Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blend ratio of 50 vol. % or more and 85 vol. % or less. The filler includes a first magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material composed mainly of Ni, the first magnetic filler having a first grain size distribution, and a second magnetic filler having a second grain size distribution different from the first grain size distribution.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: April 23, 2019
    Assignee: TDK CORPORATION
    Inventor: Kenichi Kawabata
  • Patent number: 10270025
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Shih-Chang Liu, Chern-Yow Hsu, Kuei-Hung Shen
  • Patent number: 10255962
    Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device also utilizes an external magnetic field generator, thereby allowing efficient writing of the bit without a concomitant increase in read disturb.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: April 9, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Mourad El Baraji, Kadriye Deniz Bozdag, Marcin Jan Gajek, Michail Tzoufras
  • Patent number: 10255934
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula AGa2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 9, 2019
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Patent number: 10255960
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element; and a first circuit configured to control writing to the memory cell. The first circuit is configured to generate a first pulse of a second signal based on a first signal from outside, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse. A falling edge of the first pulse is based on a rising edge of the second pulse. A write pulse is output based on the fourth signal.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Shimizu
  • Patent number: 10256397
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Patent number: 10256194
    Abstract: Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold resin covering the surface of the substrate so as to embed therein the electronic component. The magnetic mold resin includes a resin material and a filler blended in the resin material in a blended ratio of 30 vol. % or more to 85 vol. % or less. The filler includes a magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material contained mainly of Ni, thereby a thermal expansion coefficient of the magnetic mold resin is 15 ppm/° C. or less.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 9, 2019
    Assignee: TDK CORPORATION
    Inventor: Kenichi Kawabata
  • Patent number: 10249815
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Jin-Won Park
  • Patent number: 10243139
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic metal layer interposed between the first ferromagnetic layer and the second ferromagnetic layer. The first ferromagnetic layer and the second ferromagnetic layer include a Heusler alloy consisting of a CoMnSi alloy. A ratio x of Mn with respect to Co2 in each of the first ferromagnetic layer and the second ferromagnetic layer is 0.7?x?1.7. Compositions of the first ferromagnetic layer and the second ferromagnetic layer are different from each other.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 26, 2019
    Assignee: TDK CORPORATION
    Inventors: Kazuumi Inubushi, Katsuyuki Nakada
  • Patent number: 10243020
    Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10236441
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer has a spinel structure in which cations are arranged in a disordered manner, and the tunnel barrier layer is expressed by a composition formula of (M1-xZnx)((T1)2-y(T2)y)O4 wherein M represents a non-magnetic divalent cation other than Zn, each of T1 and T2 represents a non-magnetic trivalent cation, and x and y represent a composition ratio in a region where composition ratios combined as follows ((1) to (5)) are vertexes, and the vertexes are connected by straight lines: (1) x=0.2, y=0.1, (2) x=0.8, y=0.1, (3) x=0.8, y=1.7, (4) x=0.6, y=1.7, and (5) x=0.2, y=0.7.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 19, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10224067
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 5, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10209323
    Abstract: Ferromagnetic Group III-V semiconductor/non-magnetic Group III-V semiconductor heterojunctions, with a magnetodiode device, to detect heterojunction magnetoresistance responsive to an applied magnetic field.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 19, 2019
    Assignee: Northwestern University
    Inventors: Bruce W. Wessels, Steven J. May
  • Patent number: 10205093
    Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 12, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventor: Yigong Wang
  • Patent number: 10205090
    Abstract: A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern. The insulation pattern may include an upper portion and a lower portion whose width is greater than a width of the upper portion.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yil-hyung Lee, Jong-Kyu Kim, Jongsoon Park, Jongchul Park
  • Patent number: 10199431
    Abstract: A device that includes a magnetic memory device, includes a magnetic tunnel junction pattern on a substrate and a mask structure on the magnetic tunnel junction pattern. The mask structure includes a conductive pattern and a sacrificial pattern, where the conductive pattern is between the magnetic tunnel junction pattern and the sacrificial pattern, and the sacrificial pattern includes a material having an etch selectivity with respect to the conductive pattern. The device includes an upper contact plug in contact with a surface of the conductive pattern of the mask structure. The device includes a lower interlayered insulating layer covering a cell region and a peripheral circuit region of the substrate, where the lower interlayered insulating layer on the cell region has a recessed top surface between adjacent magnetic tunnel junction patterns.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daeeun Jeong
  • Patent number: 10199433
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Alvin Oliver Glova, Joon-Seop Sim
  • Patent number: 10193060
    Abstract: An MRAM device may include an insulating interlayer structure, a lower electrode contact structure and a variable resistance structure. The insulating interlayer may be formed on a substrate. The lower electrode contact structure may extend through the insulating interlayer. The lower electrode contact structure may include a first electrode having a pillar shape and a second electrode having a cylindrical shape on the first electrode. An upper surface of the second electrode may have a ring shape. A variable resistance structure may be formed on the second electrode. The variable resistance structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode sequentially stacked.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Sung Han, Ki-Seok Suh, Woo-Jin Kim
  • Patent number: 10193062
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al. Methods are also provided for forming composite free layers where interfacial perpendicular anisotropy is generated therein by contact of the free layer with oxidized materials.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: January 29, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10186746
    Abstract: A waveguide for spin wave (SW) transmission, a method of fabricating a waveguide for SW transmission, and a method of transmitting an SW. The waveguide comprises a plurality of nanomagnetic material elements, each nanomagnetic material element having a respective predetermined geometric shape such that each nanomagnetic material element exhibits a deterministic ground state initializable by a magnetic field applied across the waveguide; wherein the nanomagnetic material elements are disposed relative to each other for dipolar coupling between adjacent nanomagnetic material elements.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 22, 2019
    Assignee: National University of Singapore
    Inventors: Arabinda Haldar, Dheeraj Kumar, Adekunle Adeyeye
  • Patent number: 10177305
    Abstract: Devices are described that include a multi-layered structure that is non-magnetic at room temperature, and which comprises alternating layers of Co and at least one other element E (such as Ga, Ge, and Sn). The composition of this structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55. The structure is in contact with a first magnetic layer that includes a Heusler compound. An MRAM element may be formed by overlying, in turn, the first magnetic layer with a tunnel barrier, and the tunnel barrier with a second magnetic layer (whose magnetic moment is switchable). Improved performance of the MRAM element may be obtained by placing a pinning layer between the first magnetic layer and the tunnel barrier.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jaewoo Jeong, Stuart S. P. Parkin, Mahesh G. Samant
  • Patent number: 10177303
    Abstract: A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Nishtha Sharma, Peter Dowben, Andrew Marshall
  • Patent number: 10176831
    Abstract: In one general embodiment, a method includes forming a first magnetic layer, forming a tunnel barrier layer above the first magnetic layer, and forming a second magnetic layer above the tunnel barrier layer. The tunnel barrier layer includes crystalline alumina. The tunnel barrier layer is formed at a temperature of less than 100 degrees centigrade.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Calvin S. Lo, Teya Topuria
  • Patent number: 10170518
    Abstract: Magnetic junctions usable in a magnetic device and a method for providing the magnetic junctions are described. A patterned seed layer is provided. The patterned seed layer includes magnetic seed islands interspersed with an insulating matrix. At least a portion of the magnetoresistive stack is provided after the patterned seed layer. The magnetoresistive stack includes at least one magnetic segregating layer. The magnetic segregating layer(s) include at least one magnetic material and at least one insulator. The method anneals the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates. The constituents of the magnetic segregating layer segregate such that portions of magnetic material(s) align with the magnetic seed islands(s) and such that portions of the insulator(s) align with the insulating matrix.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Vladimir Nikitin, Dmytro Apalkov, Sebastian Schafer
  • Patent number: 10163976
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Suh, Jae-Chul Shim, Kil-Ho Lee, Yong-Seok Chung, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10164169
    Abstract: The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Patent number: 10164077
    Abstract: The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Adrien Vaysset, Mauricio Manfrini
  • Patent number: 10164174
    Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 25, 2018
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Shoji Ikeda, Mathias Bersweiler, Hiroaki Honjo, Kyota Watanabe, Shunsuke Fukami, Fumihiro Matsukura, Kenchi Ito, Masaaki Niwa, Tetsuo Endoh, Hideo Ohno
  • Patent number: 10162020
    Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 25, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: William P. Taylor, Harianto Wong
  • Patent number: 10164173
    Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Man Hwang, Shi-Jung Kim, Mi-Lim Park, Jun-Soo Bae, Seung-Woo Lee
  • Patent number: 10154584
    Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 11, 2018
    Assignee: Lockheed Martin Corporation
    Inventors: Stephen Gonya, James Sean Eiche, James Patterson, Kenneth R. Twigg
  • Patent number: 10147761
    Abstract: According to one embodiment, a semiconductor memory device includes a magnetoresistive element and an insulating layer. The magnetoresistive element includes a first magnetic layer, a nonmagnetic layer, and a second magnetic layer and. The magnetoresistive element is capable of storing data according to a direction of magnetization in the first magnetic layer. The insulating layer covers a side surface of the magnetoresistive element. The first magnetic layer includes a first region and a second region. Each of the first and second regions includes a magnetic material and a nonmagnetic material. A concentration ratio of the nonmagnetic material to the magnetic material is higher in the second region than in the first region.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masatoshi Yoshikawa, Shuichi Tsubata
  • Patent number: 10147873
    Abstract: A method of forming a magnetoresistive memory device includes forming a ferromagnetic layer, forming a tunneling barrier layer on the ferromagnetic layer, forming a first preliminary free magnetic layer (free layer) containing boron (B) on the tunneling barrier layer, forming a first buffer layer on the first preliminary free layer, performing a first annealing process to transition the first preliminary free layer to form a second preliminary free layer and the first buffer layer to form a first boride layer, performing an etching process to remove the first boride layer, forming a second buffer layer on the second preliminary free layer, performing a second annealing process to transition the second preliminary free layer to form a free layer and the second buffer layer to form a second boride layer, and performing an oxidation process to transition the second boride layer to an oxide layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonmyoung Lee, Youngman Jang, Kiwoong Kim, Yongsung Park
  • Patent number: 10141498
    Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 27, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jon M. Slaughter, Han-Jong Chia
  • Patent number: 10141067
    Abstract: According to the embodiment, a magnetic memory device includes a magnetic body. The magnetic body includes first and second extending regions, and a first connecting region. The first extending region spreads along a first direction and along a second direction crossing the first direction, and includes first and second end portions extending in the first direction. The second end portion is separated from the first end portion in the second direction. The second extending region spreads along the first direction and along a third direction crossing the first direction, and includes third and fourth end portions extending in the first direction. The fourth end portion is separated from the third end portion in the third direction. The first connecting region is provided between the first and third end portions, and connects the first end portion with the third end portion.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Tsuyoshi Kondo, Hirofumi Morise, Takuya Shimada, Yasuaki Ootera, Masaki Kado, Shiho Nakamura
  • Patent number: 10135392
    Abstract: The present invention relates to a spin torque oscillator with high power output and its applications. A spin torque oscillator may include a first magnetic reference layer having a fixed magnetization, a magnetic precession layer having a magnetization capable of precessing about an initial direction, and a first barrier layer interposed between the first magnetic reference layer and the magnetic precession layer. The first barrier layer is formed of an insulating material capable of inducing a negative differential resistance for the spin torque oscillator.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 20, 2018
    Assignee: INSTITUTE OF PHYSICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hongxiang Wei, Jiafeng Feng, Xiaoguang Zhang, Houfang Liu, Xiufeng Han
  • Patent number: 10133689
    Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
  • Patent number: 10134981
    Abstract: A magnetic tunnel junction (MTJ) that avoids electrical shorts and has improved data retention is disclosed. An uppermost capping layer has a first sidewall that is coplanar with an interface between outer oxidized portions and a center ferromagnetic portion of a free layer (FL) that has a FL width (FLW). A dielectric spacer is formed on the first sidewall and oxidized outer FL portions. The pinned layer (PL) has a width (PLW) substantially greater than FLW, and a second sidewall thereon is formed by a self-aligned etch using the dielectric spacer and capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and dielectric spacer but does not degrade MTJ properties since the sidewall layer does not contact the FL and PL center portions responsible for device performance. PL width>FLW ensures greater capability for data retention especially for FLW<60 nm.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 20, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang