Abstract: A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

Abstract: A signal isolator for providing at an output thereof representations of input currents from a source provided in an input conductor supported on a substrate having a bridge circuit suited for electrical connection to a source of electrical energization with a pair of series circuit members electrically connected in parallel with one another supported on a substrate with each series circuit member having a magnetoresistive member electrically connected in series with a current value controller, controlled at a controller terminal, at an output terminal of that controller. Each magnetoresistive members is electrically isolated from the input conductor and has a resistance versus applied external magnetic field characteristic that is substantially linear for at least relatively small externally applied magnetic fields.

Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

Abstract: Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first substrate and comprise a width extending over at least two of the plurality of conductive traces. A plurality of vias extend from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.

Abstract: A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the write module and the read module has a free layer that functions as a shared storage layer for both the read module and the write module. The shared storage layer receives spin torque from both the read module and the write module and has a magnetization that is rotatable by the write current.

Abstract: A semiconductor device including a Hall effect sensor and related method. The Hall effect device includes a substrate having a first conductivity type and an epitaxial layer having a second conductivity type defining a Hall effect portion. A conductive buried layer having the second conductivity type is situated between the epitaxial layer and the substrate. First and second output terminals and first and second voltage terminals are provided, with the second voltage terminal being coupled to the conductive buried layer.

Abstract: A magnetoresistive element of an aspect of the present invention including a lower electrode provided on an insulating layer on a semiconductor substrate, a first ferromagnetic layer provided on the lower electrode, a first tunnel barrier layer provided on the first ferromagnetic layer, a second ferromagnetic layer provided on the first tunnel barrier layer, and an upper electrode provided on the second ferromagnetic layer, wherein the upper electrode has a hexagonal cross-sectional shape, and a maximum size of the upper electrode in a first direction is larger than a size of the first tunnel barrier layer in the first direction, the first direction being horizontal relative to a surface of the semiconductor substrate.

Abstract: The magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. The layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of the layers. The layer of non-magnetic material induces an antiferromagnetic coupling field between the layers made of a magnetic material, the direction and amplitude of this field attenuating the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between the magnetic layers.

Abstract: A Hall-effect magnetic sensor comprises a p-type Hall element and an n-type epitaxial Hall element. The p-type element can be implanted directly on top of the n-type element. The merged Hall elements can be biased in parallel to provide a nearly zero-bias depletion layer throughout for isolation. Electrical contacts to the n-type element can be diffused down through the p-type element and positioned to partially obstruct current flow in the p-type element. Electrical contacts can be diffused into the p-type element. Each bias contact of the p-type element can be connected to respective bias contacts of the n-type element in a parallel fashion. Then, an output signal can be taken at the sense contacts of the n-type element in order to provide improved magnetic responsivity. Further provided is a method for manufacturing the Hall-effect magnetic sensor.

Abstract: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.

Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.

Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: A vertical Hall sensor which is integrated in a semiconductor chip has at least 6 electric contacts which are arranged along a straight line on the surface of the semiconductor chip. The electric contacts are wired according to a predetermined rule, namely such that when the contacts are numbered through continuously and repeatedly with the numerals 1, 2, 3 and 4 starting from one of the two outermost contacts, the contacts to which the same numeral is assigned are electrically connected with each other.

Abstract: A bipolar spin transistor is provided. In one embodiment of the present invention, the bipolar spin transistor includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type that is different from the first conductivity type and also having a spin polarization, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a first charge depletion layer therebetween, the first charge depletion layer having a first side facing the first semiconductor region and an opposing second side facing the second semiconductor region.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.

Abstract: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

Abstract: An arrangement of magnetic liners for the bit lines or word lines of an MRAM device that reduces or eliminates stray magnetic fields at the ends of the magnetic liners, thereby reducing the occurrence of offset fields over portions of the MRAM device due to the magnetic liners is described. The orientation of magnetization of adjacent magnetic liners is alternated, causing the end poles of the magnetic liners to cancel each other. The shapes of the ends of the magnetic liners are alternated to vary their switching fields. Methods are described that use this ability to vary the switching fields to alternate the orientation of magnetization of the magnetic liners.

Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Abstract: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um2 is achieved when a CoFe AP2 layer, MgO (NOX) tunnel barrier, and CoFe/NiFe free layer are used in the TMR stack. Improved RA uniformity and less head noise are observed. Optionally, a CoFe layer may be inserted between the coupling layer and CoFeB or CoFeB alloy layer to improve pinning strength and enhance crystallization.

Abstract: An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.

Abstract: An integrated circuit includes a first plate-shaped part and at least a plate-shaped second part separate from the first part and attached to the first part by deformable mechanical connection defining a non-zero angle with the first part. A method of producing the integrated circuit includes depositing deformable connecting means in contact with a first portion of the structure and a second portion of the structure, etching the structure to separate the first portion and the second portion, relatively moving the first and second portions to deform the connecting means and fastening together the first portion and the second portion.

Abstract: One embodiment relates to a method of manufacturing a magnetic sensor. In the method, an engagement surface is provided. A magnet body is formed over the engagement surface by gradually building thickness of a magnetic material. The magnet body has a magnetic flux guiding surface that substantially corresponds to the engagement surface. Other apparatuses and methods are also set forth.

Abstract: A sensing apparatus includes a holding substrate, a sensing chip and a protection layer. The sensing chip is mounted on the holding substrate and electrically connected to the holding substrate. The sensing chip has a sensing region and a non-sensing region other than the sensing region. The sensing region senses image data of an object and thus generates a sensed signal outputted to the holding substrate. The protection layer is formed by a packaging material and is simultaneously processed and integrally formed to cover the sensing region and the non-sensing region of the sensing chip and the holding substrate. The protection layer has an exposed upper surface, which has one portion serving as a sensing surface in contact with the object. The entire protection layer is composed of the same material.

Abstract: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um2 is achieved when a CoFe AP2 layer, MgO (NOX) tunnel barrier, and CoFe/NiFe free layer are used in the TMR stack. Improved RA uniformity and less head noise are observed. Optionally, a CoFe layer may be inserted between the coupling layer and CoFeB or CoFeB alloy layer to improve pinning strength and enhance crystallization.

Abstract: A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.

Abstract: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ?10 ohm/?m2.

Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A magnetic sensor comprises a plurality of layers including a substrate having circuitry, at least one conductive layer to interconnect the circuitry, and an insulator layer to electrically insulate the at least one conductive layer. First and second conductive layers are disposed above the substrate with a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor. A first terminal is electrically connected to the first conductive layer and a second terminal is electrically connected to the second conductive layer.

Abstract: A toggle-MRAM device is disclosed that uses an SAF composite and lowers the operating field substantially with a wide operating field margin and high thermal stability using specific magnetic parameters. Consequently, this device enhances the performance of MRAM's, especially in its large operating field margin and high thermal stability characteristics with a low current.

Abstract: Tunneling magnetoresistive (TMR) electrical lapping guides (ELG) are disclosed for use in wafer fabrication of magnetic sensing devices, such as magnetic recording heads using TMR read elements. A TMR ELG includes a TMR stack comprising a first conductive layer, a barrier layer, and a second conductive layer of TMR material. The TMR ELG also includes a first lead and a second lead that connect to conductive pads used for applying a sense current to the TMR ELG in a current in plane (CIP) fashion. The first lead contacts one side of the TMR stack so that the first lead contacts both the first conductive layer and the second conductive layer of the TMR stack. The second lead contacts the other side of the TMR stack so that the second lead contacts both the first conductive layer and the second conductive layer of the TMR stack.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a capping layer has a bilayer configuration with a non-magnetic NiFeX inner layer on a NiFe free layer and a Ta layer on the NiFeX layer to improve dR/R and minimize magnetostriction. Optionally, a trilayer configuration may be employed where the Ta layer is sandwiched between an inner NiFeX layer and an outer Ru layer. The X component in NiFeX is preferably an element having an oxidation potential greater than Ni or Fe such as Mg, Hf, Zr, Nb, or Ta. NiFeX is preferably formed by co-sputtering a NiFe target with an X target at a forward power of about 200 W and 50 W, respectively. In an MRAM structure, the Mg content in NiFeMg may be increased to >50 atomic % to improve the gettering power of removing oxygen from the free layer.

Abstract: The addition of segmented write word lines to a spin-transfer MRAM structure serves to magnetically bias the free layer so that the precessional motion of the magnetization vector that is set in play by the flow of spin polarized electrons into the free layer allows said magnetic vector to be switched rather than to oscillate between two easy axis directions.

Abstract: A method and system include providing a single pinned layer, a free layer, and a spacer layer between the pinned and free layers. The spacer layer is nonmagnetic. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element. The free layer is a simple free layer. In one aspect, the method and system include providing a spin engineered layer adjacent to the free layer. The spin engineered layer is configured to more strongly scatter majority electrons than minority electrons. In another aspect, at least one of the pinned, free, and spacer layers is a spin engineered layer having an internal spin engineered layer configured to more strongly scatter majority electrons than minority electrons. In this aspect, the magnetic element may include another pinned layer and a barrier layer between the free and pinned layers.

Abstract: A high density integrated processing and sensing chip includes an integrated signal processing circuit formed on one side of a substrate and a magnetic sensor element formed on an opposing side of the substrate. In one embodiment, the integrated signal processing circuit and the magnetic sensor are able to electrically connected to one another through vias or through metallic trace elements provided by a package frame.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/?5 Angstroms.

Abstract: An integrated sensor has a magnetic field sensing element and first and second relatively high magnetically permeable members forming a gap, wherein the magnetic field element is disposed within the gap. The magnetically permeable members provide an increase in the flux experienced by the magnetic field sensing element in response to a magnetic field. The integrated sensor can be used as a current sensor, a proximity detector, or a magnetic field sensor.

Abstract: A pin junction element includes a ferromagnetic p-type semiconductor layer and a n-type semiconductor layer which are connected via an insulating layer, and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer and the magnetization of the ferromagnetic n-type semiconductor layer. In this pin junction element, an empty layer is formed with an applied bias, thereby generating tunnel current via an empty layer. As a result, it is possible to generate tunnel current even when adopting a thicker insulating layer than that of the conventional tunnel magnetic resistance element.

Abstract: A magnetic random access memory described in embodiments of the present invention comprises a conductive line, a soft magnetic material which surrounds the conductive line, a gap disposed in a part of the soft magnetic material, and a magneto-resistive element in which a part of a vertical magnetization film as a magnetic free layer is positioned in the gap and in which a vertical magnetization film as a magnetic pinned layer is positioned outside the gap.

Abstract: A semiconductor chip includes a first functional element having a first electronic functional-element parameter exhibiting a dependence relating to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a first output signal, a second functional element having a second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal exhibiting a predefined dependence on the mechanical stress present in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that that the first and second functional-element stress influence functions ar

Abstract: At least one magnetic field sensing device and an RF transceiver are integrated in a discrete, single-chip package. Rather than requiring at least two separate chips to wirelessly transmit the device output, an integrated, single chip solution can be used. The single chip integration of the at least one magnetic field sensing device and the RF transceiver can reduce the physical space required and, therefore, allow such devices to be smaller, lighter, and possibly more portable.

Abstract: A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni˜0.8Fe˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher anisotropy sub-layer. When a field is applied at <10° angle from the easy axis, magnetic vectors for the two sub-layers rotate to form different angles from the easy axis. A method is also described for selectively writing to bits along a word line that is orthogonal to bit line segments and avoids the need to “read first”. A bipolar word line pulse with two opposite pulses separated by a no pulse interval is applied in the absence of a bit line pulse to write a “0”. A bit line pulse opposite the second word line pulse writes a “1”.

Abstract: A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a given strength may be applied to at least a portion of the magneto-resistant transistor, the given strength determining a resistance in the at least a portion of the magneto-resistant transistor. Thus, by adjusting the given strength of the magnetic field, the resistance may be adjusted. Therefore, different emitter current inputs may be achieved with a fixed voltage. Further, a base current may vary with a controlled variation of the emitter current input.

Abstract: A ferromagnetic thin-film based magnetic field detection system having a substrate supporting a magnetic field sensor in a channel with a first electrical conductor supported on the substrate positioned at least in part along the channel gap and in direct contact with at least some surface of the magnetic field sensor ands a second electrical conductor supported on the substrate positioned at least in part along the channel gap in a region thereof adjacent to, but separated from, the magnetic field sensor.