With Housing Or Encapsulation Patents (Class 257/433)
  • Patent number: 10378736
    Abstract: An LED bracket, LED bracket array, LED device and LED display screen are disclosed. The LED bracket includes a PCB circuit substrate and an insulating material. The PCB circuit substrate includes at least two electrically insulated electrode regions. Each electrode region includes a top electrode region, a side electrode region and a bottom electrode region. The side electrode region connects the top electrode region and the bottom electrode region into an integrated structure. The side electrode region is a side surface sunk from outside to an inner part of the PCB circuit substrate. The insulating material is filled in the side electrode region. An upper end surface and a lower end surface of the insulating material do not exceed an upper surface and a lower surface of the PCB circuit substrate. A thickness of the insulating material is less than a thickness of the PCB circuit substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Foshan NationStar Optoelectronics Co., Ltd.
    Inventors: Chuanbiao Liu, Feng Gu, Yuanbin Lin, Xiangling Luo, Xiaofeng Liu, Xi Zheng, Yan Liu
  • Patent number: 10347774
    Abstract: A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 9, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Noriyuki Kishi, Tatsuhiro Koizumi, Hiroyuki Shiraki, Mitsuru Tamashiro, Masaya Yamamoto
  • Patent number: 10304815
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10298818
    Abstract: A camera for a vision system for a vehicle includes an imager chip having an at least partially light transmitting substrate having a photosensor array disposed at a second surface of the at least partially light transmitting substrate so as to sense light that passes through the at least partially light transmitting substrate. The imager chip includes electrically conductive pads disposed at the second surface of the at least partially light transmitting substrate. A circuit element includes circuitry disposed at least at a third surface thereof. The imager chip is mounted at the circuit element with the second surface of the at least partially light transmitting substrate opposing the third surface of the circuit element. Electrical connection between the electrically conductive pads and the circuitry of the circuit element is made when mounting the imager chip at the circuit element.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 21, 2019
    Assignee: MAGNA ELECTRONICS INC.
    Inventor: Christopher L. Van Dan Elzen
  • Patent number: 10288985
    Abstract: An imaging device having a lens group; a lens barrel holding the lens group; a base member holding the lens barrel; an imaging element; a fixed plate arranged facing at least part of the base member in a state in which the imaging element is fixed; and a pressing member for attaching, to the base member, the fixed plate in a state in which the fixed plate is temporarily fixed to the base member in a state in which fixed plate is movable in a direction intersecting the axial line of the lens group, relative to the base member.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 14, 2019
    Assignee: Nidec Copal Corporation
    Inventors: Yuta Nakamura, Ryo Kikuta
  • Patent number: 10276506
    Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10269852
    Abstract: A device includes a first integrated circuit containing a photodiode and a first metal interconnect structure connected to the photodiode, and a second integrated circuit containing a transistor and a second metal interconnect structure connected to the transistor. The first integrated circuit and the second integrated circuit are connected together through the first metal interconnect structure and the second metal interconnect structure. Since no transistor is present around the photodiode, the photodiode has an increased photosensitive area and an improved fill factor, resulting in an increase of the quantum efficiency, higher integration and lower consumption of the image sensor.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Jerry Liu, Phil Wu, Herb He Huang
  • Patent number: 10217879
    Abstract: The present invention provides an optical semiconductor device in which damage of a lens when being mounted and mounting displacement due to suction failures of a chip can be suppressed. An optical semiconductor device according to an embodiment includes: a semiconductor substrate having a first surface and a second surface facing the first surface; an electrode formed over the first surface of the semiconductor substrate; an optical element that is electrically coupled to the electrode and is formed in the semiconductor substrate; and a lens arranged on the second surface side of the optical element. A concave part is formed in the second surface of the semiconductor substrate, and the lens is arranged at the bottom of the concave part. A top part on the second surface side of the lens is located on the first surface side relative to the second surface located around the concave part.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshito Taniguchi
  • Patent number: 10211249
    Abstract: An x-ray detector includes a substrate including an electrically conductive connection between a read-out contact in the region of the top side of the substrate and an input of a pre-amplifier in an active layer of an integrated circuit. A first electrically conductive connection is provided between the read-out contact and a second electrically conductive connection. A surface of a first light protection is relatively larger than a surface of a light-permeable region of the first light protection. The second electrically conductive connection is provided within a second projection of the surface of the light-permeable region along the surface normal and below the second light protection. A third electrically conductive connection between the second electrically conductive connection and the pre-amplifier is provided below the second light protection. The input of the pre-amplifier is protected against direct incidence of light.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 19, 2019
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Martin Groepl, Edgar Goederer, Thomas Suttorp
  • Patent number: 10197750
    Abstract: A light guiding structure is provided. The structure includes an anodized aluminum oxide (AAO) layer and a fluoropolymer layer located immediately adjacent to a surface of the AAO layer. Light propagates through the AAO layer in a direction substantially parallel to the fluoropolymer layer. An optoelectronic device can be coupled to a surface of the AAO layer, and emit/sense light propagating through the AAO layer. Solutions for fabricating the light guiding structure are also described.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10183858
    Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Albert Wan, Yu-Sheng Hsieh, Chao-Wen Shih, Shou Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10177098
    Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Patent number: 10170440
    Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad, and a second bonding pad on a top surface of the stacking structure, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 ?m; a carrier comprising a connecting surface; a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and a conductive connecting layer comprising a current conductive area between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 1, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
  • Patent number: 10157274
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10156717
    Abstract: In an electro-optical device, light is incident on a mirror by penetrating a cover, and the light reflected by the mirror is emitted by penetrating the cover. Here, the cover includes a first light-transmitting plate and a second light-transmitting plate facing the first light-transmitting plate, and a gap which is open toward both sides in a first direction is provided between the first light-transmitting plate and the second light-transmitting plate due to a spacer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 18, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yasuo Yamasaki
  • Patent number: 10153235
    Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Kwon Jung, Bang Chul Ko, Chul Choi, Jung Hyun Cho, Joo Hwan Jung, Yong Ho Baek, Seung Eun Lee
  • Patent number: 10141286
    Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Il Lee, Cha-Jea Jo, Ji-Hwang Kim
  • Patent number: 10134961
    Abstract: Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In one aspect, a method of providing a submount based light emitter component can include providing a ceramic based submount, providing at least one light emitter chip on the submount, providing at least one electrical contact on a portion of the submount, and providing a non-ceramic based reflector cavity on a portion of the submount.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 20, 2018
    Assignee: Cree, Inc.
    Inventors: Jesse Colin Reiherzer, Christopher P. Hussell
  • Patent number: 10134957
    Abstract: A surface-mountable optoelectronic semiconductor component is specified. The surface-mountable optoelectronic semiconductor component includes an optoelectronic semiconductor chip, a radiation-transmissive growth substrate, a housing body and an electrically conductive connection. The housing body is arranged at least in places between a side surface of the growth substrate and the electrically conductive connection. The housing body completely covers all of the side surfaces of the growth substrate, and the housing body has, on a surface facing away from the side surface of the growth substrate, traces of material removal or traces of a form tool.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: November 20, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Norwin von Malm
  • Patent number: 10129452
    Abstract: A camera module and an array camera module based on an integral packing process are disclosed. The camera module or each of the camera module units of the array camera module includes a circuit board, an integral base, a photosensitive element operatively connected to the circuit board, a lens, a light filter holder installed at the integral base and a light filter installed at the light filter holder. The light filter is not required to be directly installed to the integral base, so that the light filter is protected and the requiring area of the light filter is reduced.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: November 13, 2018
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Nan Guo, Takehiko Tanaka
  • Patent number: 10084135
    Abstract: An illumination device includes a substrate, a light emitting structure, a sealant, and a laminating board is provided. The light emitting structure includes a first electrode layer, a light emitting layer and a second electrode layer stacked on the substrate sequentially. The sealant covers the light emitting structure. The laminating board is attached to the substrate. The sealant is located between the laminating board and the substrate. The laminating board includes a carrier body, a metal layer and a plurality of pads. The metal layer is exposed at a first surface of the carrier body, is in contact with the sealant and shields an area of the light emitting layer of the light emitting structure. The pads are exposed at the first surface of the carrier body and electrically connected to the first electrode layer and the second electrode layer. The metal layer is electrically isolated from the pads.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 25, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Hsuan-Yu Lin, Hsin-Chu Chen, Wen-Hong Liu, Chao-Feng Sung, Chun-Ting Liu, Je-Ping Hu, Wen-Yung Yeh
  • Patent number: 10083939
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10078007
    Abstract: An infrared sensor includes an infrared detecting device, a lens, a member, a gap and a spacer. The lens is disposed above the infrared detecting device. The member forms an external surface and includes a first opening having a maximum internal diameter. The gap is disposed between the member and the lens. The spacer is disposed between the member and the lens so as to form the gap, and that is directly contact with lens. The spacer has a circular inner periphery, in planar view, which has a larger internal diameter than the maximum internal diameter of the first opening of the member.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 18, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takafumi Okudo, Takahiro Miyatake, Yoshiharu Sanagawa, Masao Kirihara, Yoichi Nishijima, Takanori Aketa, Ryo Tomoida
  • Patent number: 10079198
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 18, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
  • Patent number: 10060820
    Abstract: Suspending a microelectromechanical system (MEMS) pressure sensing element inside a cavity using spring-like corrugations or serpentine crenellations, reduces thermally-mismatched mechanical stress on the sensing element. Overlaying the spring-like structures and the sensing element with a gel further reduces thermally-mismatched stress and vibrational dynamic stress.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Shiuh-Hui Steven Chen, Jen-Huang Albert Chiou, Robert C. Kosberg, Daniel Roy Empen
  • Patent number: 10020343
    Abstract: Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 10, 2018
    Assignee: FLIR Systems, Inc.
    Inventors: Edward K. Huang, Andrew D. Hood, Bryan Gall, Paula Heu, Richard E. Bornfreund
  • Patent number: 9991621
    Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 5, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Konrad Wagner, Jürgen Holz
  • Patent number: 9972729
    Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 15, 2018
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Patent number: 9955055
    Abstract: An array imaging module includes at least two optical lenses and a molded photosensitive assembly, wherein the molded photosensitive assembly includes at least two photosensitive units, a circuit board that electrically couples to the photosensitive units, and a molded base having at least two optical windows. The molded base is integrally coupled at the circuit board at a peripheral portion thereof, wherein the photosensitive units are aligned with the optical windows respectively. The optical lenses are located along two photosensitive paths of the photosensitive units respectively, such that each of the optical windows forms a light channel through the corresponding photosensitive unit and the corresponding optical lens.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 24, 2018
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Takehiko Tanaka, Nan Guo, Zhen Huang, Duanliang Cheng, Liang Ding, Feifan Chen, Heng Jiang
  • Patent number: 9910147
    Abstract: A radar antenna is provided. The radar antenna includes a radar case having a front side and a rear side, a signal processor provided inside the radar case and configured to perform signal processing on a reception signal that is received by an EM radiator configured to transceive an electromagnetic wave, and a wireless LAN antenna fixed inside the radar case, having a horizontal directivity, and configured to transmit the reception signal processed by the signal processor to an external terminal device, the wireless LAN antenna being oriented such that a direction of the horizontal directivity of the wireless LAN antenna is in parallel to the front-and-rear directions of the radar case.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: March 6, 2018
    Assignee: Furuno Electric Co., Ltd.
    Inventors: Koji Atsumi, Dai Takemoto, Tetsuya Miyagawa
  • Patent number: 9911726
    Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventor: Philip G. Emma
  • Patent number: 9904776
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 9892304
    Abstract: A fingerprint identification device includes a fingerprint identification controller and a fingerprint identification sensor. The fingerprint identification sensor includes a substrate having a top surface, a bottom surface opposite to the top surface, and a side surface coupled between the top surface and the bottom surface. Sensor electrodes are arranged on the top surface, electrical leads couple the sensor electrodes and the fingerprint identification controller. The coupling leads extend from the top surface along the side surface to the bottom surface.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 13, 2018
    Assignees: INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Te Chang, Chia-Chun Tai, Wei-Chung Chuang, Yen-Heng Huang
  • Patent number: 9874486
    Abstract: Systems and methods for packaging a MEMS device are provided. Embodiments herein avoid the use of a metal housing enclosing the MEMS device or die pad of the MEMS device. Instead, a metal port is mounted directly to the MEMS device using a ceramic carrier. In preferred embodiments, the ceramic carrier is soldered, brazed, welded or eutectic bonded to the metal port.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: January 23, 2018
    Assignee: DUNAN SENSING, LLC
    Inventors: Gary Winzeler, Danny Do, Cuong D. Nguyen, Emir Vukotic
  • Patent number: 9846067
    Abstract: A flow sensor structure seals the surface of an electric control circuit and part of a semiconductor device via a manufacturing method that prevents occurrence of flash or chip crack when clamping the semiconductor device via a mold. The flow sensor structure includes a semiconductor device having an air flow sensing unit and a diaphragm, and a board or lead frame having an electric control circuit for controlling the semiconductor device, wherein a surface of the electric control circuit and part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed. The flow sensor structure may include surfaces of a resin mold, a board or a pre-mold component surrounding the semiconductor device that are continuously not in contact with three walls of the semiconductor device orthogonal to a side on which the air flow sensing unit portion is disposed.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 19, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsutomu Kono, Yuuki Okamoto, Takeshi Morino, Keiji Hanzawa
  • Patent number: 9838579
    Abstract: A method for producing a camera includes: mounting an image sensor on a circuit carrier and contacting with a power device for recording image signals of the image sensor; measuring an objective while ascertaining a tilting angle of its optical axis in terms of an amount and azimuth; providing an objective holder having a tube and locating pins; placing the objective holder with its locating pins on at least one of the circuit carrier and the image sensor; inserting the objective in a specified rotational position or at an azimuth angle into the tube as a function of the ascertained tilting angle; and adjusting the focus. An axis of symmetry of the tube of the objective holder has a counter-tilting angle with respect to a surface normal of the image sensor, which is the opposite of the ascertained tilting angle or the image shell tilting of the objective.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 5, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventor: Martin Reiche
  • Patent number: 9806056
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Patent number: 9791990
    Abstract: Embodiments of the disclosure generally provide an integrated control system having an integrated controller that is configured to provide both display updating signals to a display device and a capacitive sensing signal to a sensor electrode that is disposed within the integrated input device. The internal and/or external signal routing configurations described herein can be adapted to reduce signal routing complexity typically found in conventional devices and reduce the effect of electrical interference created by the capacitive coupling formed between the display routing, capacitive sensing routing and/or other components within the integrated control system. Embodiments can also be used to reduce electromagnetic interference (EMI) on the display and touch sensing signals received, transmitted and processed within the integrated control system.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: October 17, 2017
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Christopher A. Ludden
  • Patent number: 9780251
    Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 3, 2017
    Assignee: XINTEC INC.
    Inventors: Wei-Luen Suen, Wei-Ming Chien, Po-Han Lee, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 9780135
    Abstract: An image pickup device and a method of the same are described herein. By way of first example, the image pickup device includes a seal member having a first surface, the first surface of the seal member including a concave portion, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member. By way of a second example, the image pickup device includes a seal member having a first surface, the first surface being a polished surface, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 3, 2017
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Taizo Takachi
  • Patent number: 9773959
    Abstract: A method for manufacturing an optical-semiconductor device, including forming a plurality of first and second electrically conductive members that are disposed separately from each other on a support substrate; providing a base member formed from a light blocking resin between the first and second electrically conductive members; mounting an optical-semiconductor element on the first and/or second electrically conductive member; covering the optical-semiconductor element by a sealing member formed from a translucent resin; and obtaining individual optical-semiconductor devices after removing the support substrate.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 26, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Masato Fujitomo, Hiroto Tamaki, Shinji Nishijima, Yuichiro Tanda, Tomohide Miki
  • Patent number: 9762026
    Abstract: An optical module includes a semiconductor optical device in which an active layer located at one side, an electrode located at the same side, and a mirror that reflects light toward the side opposite the electrode are monolithically integrated, a sub-mount having one surface on which a first wiring pattern is formed, a substrate in which an optical waveguide and a grating coupler are formed in a surface layer of the substrate, a spacer having an upper surface on which a second wiring pattern is formed, and a wire. The sub-mount is mounted on the spacer. The first wiring pattern on the sub-mount faces part of the second wiring pattern on the spacer and is electrically connected thereto. The second wiring pattern on the spacer includes a pad being disposed in a region exposed from the sub-mount and being bonded to the wire.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 12, 2017
    Assignee: OCLARO JAPAN, INC.
    Inventors: Kohichi Robert Tamura, Takanori Suzuki, Mitsuo Akashi, Shigehisa Tanaka, Hiroaki Inoue, Hiroyasu Sasaki
  • Patent number: 9756696
    Abstract: A configurable LED lighting system and its method of operation are disclosed. A lighting system or apparatus includes a string of LEDs, wherein specific LEDs are operable to emit different colors of light. The string includes a plurality of series-connected color segments. A shunt segment includes additional LEDs. The LED shunt segment is connected in parallel with at least one of the color segments. A controller is connected to the LED shunt segment to selectively balance drive current between the LED shunt segment and the color segment to which it is connected in parallel so that a color temperature of light is controllable by a processor. The diverted power still produces light and power is not wasted. The controller can use a polynomial equation or a look-up table to calculate color output values.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 5, 2017
    Assignee: Cree, Inc.
    Inventor: Everett Bradford
  • Patent number: 9748218
    Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Philip G. Emma
  • Patent number: 9735139
    Abstract: The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first integrated circuit chip including light-emitting diodes; b) bonding a second integrated chip to a first surface of the first chip; c) decreasing the thickness of the first chip on the side opposite to the first surface to form a second surface opposite to the first surface; d) bonding, to the second surface, a cap including a silicon wafer provided with recesses opposite the light-emitting diodes; e) decreasing the thickness of the second chip; f) decreasing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) sawing the structure obtained at step f) into a plurality of separate optoelectronic devices.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 15, 2017
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Ivan-Christophe Robin
  • Patent number: 9691722
    Abstract: A surface mount high-frequency circuit is configured such that a plurality of ground pads 41 and a plurality of external connection ground conductors 51 are discretely disposed to surround a signal line pad 42 and an external connection signal line conductor 52, and a plurality of interlayer connection ground conductors 31 and that a plurality of columnar ground conductors 12 are discretely disposed to surround an interlayer connection signal line conductor 32. Thus, it is possible to suppress radiation of an unnecessary signal to the outside using a simple production process that is completed by only a wafer process without separately preparing a component such as a shield cover case.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Yuasa, Kiyoshi Ishida, Yoshihiro Tsukahara, Kohei Nishiguchi
  • Patent number: 9673182
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9666828
    Abstract: Provided are methods of manufacturing a substrate for an OED and an OED. According to the methods of manufacturing a substrate for forming an OED such as an OLED and an OED, a substrate for forming a device having excellent light extraction efficiency and improved reliability by preventing penetration of moisture or air into the device, or device using the same may be provided.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: May 30, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Young Eun Kim, Jong Seok Kim, Young Kyun Moon, Jin Ha Hwang
  • Patent number: 9666930
    Abstract: The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: May 30, 2017
    Assignee: NXP USA, INC.
    Inventors: Jinbang Tang, Neil T. Tracht
  • Patent number: 9659898
    Abstract: Embodiments of the present disclosure are directed towards apparatuses, systems, and methods for die attach coatings for semiconductor packages. In one embodiment, a die may be coupled with a substrate by a die attach and a coating may be applied to an edge of the die attach.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Kevin J. Anderson, Walid Meliane, John M. Beall