With Housing Or Encapsulation Patents (Class 257/433)
  • Patent number: 11502479
    Abstract: An optical device and a light-source device. The optical device includes a first substrate having a first plane and elements, and a second substrate having a second face that faces the first plane. The elements are disposed on the first substrate to emit or receive light in a direction intersecting with the first plane. The second substrate includes lenses disposed to correspond to the elements, and the second substrate extends in a first direction parallel to the second face to contact the first plane. The second substrate has a joint used to determine spacing between the first substrate and the second substrate, and the joint contacts the first substrate with an area smaller than a maximum size of cross-sectional area parallel to the second face of the joint. The light-source device includes the optical device and a driver to drive the optical device.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: November 15, 2022
    Assignee: Ricoh Company, Ltd.
    Inventors: Toshiya Yamaguchi, Masami Seto
  • Patent number: 11456286
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 11422397
    Abstract: The disclosure relates to a display assembly and a manufacturing method for the display assembly. The display assembly includes a frame, a display panel, and protective glass; wherein the display panel is attached onto the inner surface of the protective glass to form an integrated structure, an edge of the inner surface of the protective glass extends beyond the display panel, and the edge of the inner surface of the protective glass is bonded to a surface of a side wall of the frame by a bonding agent.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 23, 2022
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Jie Yang, Feng Liu, Shihwei Lu
  • Patent number: 11387220
    Abstract: A display according to one embodiment of the present invention comprises: a light-transmitting first layer and including a plurality of cavities; a plurality of light-emitting diode (LED) chips disposed in the cavities; and a second layer including a circuit electrically connected to the plurality of LED chips. Various other embodiments are also possible.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Woon Jang, Hyun-Tae Jang, Youngjun Moon, Changjoon Lee
  • Patent number: 11363174
    Abstract: A lens module includes a circuit board, a carrier, and a photosensitive chip. The carrier and the photosensitive chip are arranged on a surface of the circuit board. The carrier includes a first surface arranged facing the circuit board and a second surface facing away from the circuit board. A window is defined in the carrier penetrating the first surface and the second surface. The photosensitive chip is received in the window. The carrier, the photosensitive chip, and the circuit board cooperatively form an enclosed space. An adhesive filler is arranged in the enclosed space. At least one air hole is defined in the adhesive filler. The at least one air hole communicates an inside of the enclosed space to outside the enclosed space.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 14, 2022
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventor: Hung-Kun Wang
  • Patent number: 11355479
    Abstract: A display according to one embodiment of the present invention comprises: a light-transmitting first layer and including a plurality of cavities; a plurality of light-emitting diode (LED) chips disposed in the cavities; and a second layer including a circuit electrically connected to the plurality of LED chips. Various other embodiments are also possible.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Woon Jang, Hyun-Tae Jang, Youngjun Moon, Changjoon Lee
  • Patent number: 11335715
    Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 17, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masaya Nagata, Satoru Wakiyama
  • Patent number: 11315848
    Abstract: A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 11309277
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Patent number: 11282977
    Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 22, 2022
    Assignee: The 13th Research institute of China Electronics Technolegy Group Corporation
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie Lv, Xin Tan, Yuangang Wang, Xubo Song, Jia Li, Yulong Fang
  • Patent number: 11276615
    Abstract: A described example includes: a die with an active surface; a cap mounted over a portion of the active surface of the die; and mold compound covering the cap and covering portions of the die, the cap excluding the mold compound from contact with the portion of the active surface of the die.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Laura May Antoinette Dela Paz Clemente, Jerry Gomez Cayabyab
  • Patent number: 11275222
    Abstract: Optoelectronic systems and methods of assembly thereof are described herein according to the present disclosure. An example of an optoelectronic described herein includes a substrate and an interposer coupled to the substrate including one or more optical emitters and one or more photodetectors to be mounted thereto. The interposer is fabricated with one or more mechanical datums located on the interposer with respect to flip chip pads to position and couple the optical emitters and photodetectors to the interposer. The optoelectronic system also includes an optical connector and an optical socket that includes one or more mechanical datums corresponding to the mechanical datums of the interposer. The optical socket is configured to align the optical connector with the optical emitters and the photodetectors when the optical socket is coupled to the substrate and the optical connector is received within the optical socket.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 15, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Paul Kessler Rosenberg, Sagi Varghese Mathai, Kevin B. Leigh, Michael Renne Ty Tan
  • Patent number: 11257964
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 22, 2022
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Fu-Chou Liu, Chien-Chen Lee, Li-Chun Hung, Ya-Han Chang
  • Patent number: 11258229
    Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a sub-mount, one or more micro-devices attached to the sub-mount, and a lid attached to the sub-mount. The lid includes a dispense channel and a gel groove which allows for a thermal gel to be dispensed between the lid and the micro-device in a manner that mitigates the thermal gel dispersing and/or flowing onto components of the micro-devices.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 22, 2022
    Assignee: Cisco Technology, Inc.
    Inventor: Frederick W. Warning, Jr.
  • Patent number: 11233015
    Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Patent number: 11152541
    Abstract: A substrate according to an embodiment includes a plurality of land portions that are bonded to a plurality of terminals of a light source via solder, respectively, the light source having the terminals on a surface other than a light-emitting surface, each of the land portions having a cutout provided by cutting in accordance with a shape of the corresponding terminal.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 19, 2021
    Assignee: MINEBEA MITSUMI INC.
    Inventors: Tomotaka Horikawa, Makoto Furuta
  • Patent number: 11145961
    Abstract: An illustrative example electronic device includes a substrate integrated wave guide (SIW) comprising a substrate and a plurality of conductive members in the substrate. An antenna member is situated at least partially in the substrate in a vicinity of at least some of the plurality of conductive members. A signal generator has a conductive output electrically coupled with the antenna member. The antenna member radiates a signal into the SIW based on operation of the signal generator.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 12, 2021
    Assignee: APTIV TECHNOLOGIES LIMITED
    Inventors: George J. Purden, Shawn Shi
  • Patent number: 11081518
    Abstract: The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 3, 2021
    Assignee: NINGBO SUNNY OPOTECH CO., LTD.
    Inventors: Mingzhu Wang, Bojie Zhao, Takehiko Tanaka, Zhenyu Chen, Heng Jiang, Nan Guo
  • Patent number: 11060903
    Abstract: A camera module includes a base, a circuit board bearing the base, and a metal plate bearing the circuit board and the base. The base includes a receiving portion and a bearing portion. The bearing portion surrounds the receiving portion. The bearing portion defines a cutout to receive an electronic component of the circuit board.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 13, 2021
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventors: Shin-Wen Chen, Jian-Chao Song, Sheng-Jie Ding, Jing-Wei Li
  • Patent number: 11064612
    Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
  • Patent number: 11043270
    Abstract: Programmable devices and methods for fabricating the programmable devices are described. In an example, a method for fabricating a programmable device can include bonding a UV light source to a computer chip by flip-chip mounting the UV light source to the computer chip. The UV light source can be configured to emit UV light towards a UV erasable area of the computer chip to perform UV erasing on the computer chip. The method can further include bonding a carrier to the computer chip by flip chip mounting the computer chip to the carrier using a second array of bond pads.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Frank Robert Libsch, Ali Afzali-Ardakani, James B. Hannon
  • Patent number: 11037969
    Abstract: A solid-state imaging device includes a substrate and a photoelectric conversion region. The substrate has a charge accumulation region. The photoelectric conversion region is provided on the substrate. The photoelectric conversion region is configured to generate signal charges to be accumulated in the charge accumulation region. The photoelectric conversion region comprises a material that is not transparent.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SONY CORPORATION
    Inventors: Atsushi Toda, Teruo Hirayama
  • Patent number: 11031375
    Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Sil Lee, Dong Kwan Kim
  • Patent number: 10978508
    Abstract: A direct bonding method for infrared focal plane arrays, includes steps of depositing a thin adhesion layer on infrared radiation detecting material, removing a portion of the thin adhesion layer with a chemical-mechanical polishing process, forming a bonding layer at a bonding interface, and bonding the infrared radiation detecting material to a silicon wafer with the thin adhesion layer as a bonding layer. The thin adhesion layer may include SiOx, where x ranges between 1.0 and 2.0. The thickness of the thin adhesion layer to form the bonding layer is 500 angstrom or less.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 13, 2021
    Assignee: L3 CINCINNATI ELECTRONICS CORPORATION
    Inventors: Steven Allen, Michael Garter, Robert Jones, Joseph Meiners, Yajun Wei, Darrel Endres
  • Patent number: 10976200
    Abstract: An optical sensing device comprises a photodetector array comprising at least one first photodetector and at least one second photodetector, the photodetector array being arranged on a semiconductor substrate. The optical sensing device further comprises a filter stack arranged on the substrate and covering the photodetector array. The filter stack comprises at least two first lower dielectric mirrors and at least two second lower dielectric mirrors, where a first and a second lower mirror are arranged above the first photodetector and a first and a second lower mirror are arranged above the second photodetector, and where the first lower mirrors have a different thickness in vertical direction which is perpendicular to the main plane of extension of the substrate than the second lower mirrors. The filter stack further comprises a spacer stack arranged on the first and second lower mirrors, and an upper dielectric mirror arranged on the spacer stack and covering the photodetector array.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 13, 2021
    Assignee: AMS AG
    Inventors: Hubert Enichlmair, Gerhard Eilmsteiner
  • Patent number: 10930604
    Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 23, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nurul Nadiah Manap, Shutesh Krishnan, Soon Wei Wang
  • Patent number: 10921945
    Abstract: The present invention provides a resistive force touch control device. The resistive force touch control device includes a first substrate and a second substrate spaced facing one another, a plurality of first wires parallelly spaced from one another and disposed on one side of the first substrate facing the second substrate, a plurality of second wires parallelly spaced from one another and disposed on one side of the second substrate facing the first substrate, and first anisotropic conductive adhesive located between the plurality of first wires and the plurality of second wires, wherein the plurality of first wires intersects the plurality of second wires. Therefore, force touch can be realized.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 16, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoliang Feng
  • Patent number: 10908324
    Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 2, 2021
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Takehiko Tanaka, Nan Guo, Zhenyu Chen, Heng Jiang, Zhongyu Luan, Fengsheng Xi, Feifan Chen, Liang Ding
  • Patent number: 10877231
    Abstract: The present disclosure is drawn to wirebonding for optical engines having side-mounted optoelectronic components. An integrated circuit is mounted on a first surface of a substrate block, and an optoelectronic component is positioned on a second surface of the substrate block and is oriented to emit light in a direction parallel to a plane defined by the first surface. A wirebond is drawn between the integrated circuit and a base substrate on which the substrate block is mounted. A optoelectronic component is then contacted with the wirebond, and a portion of the wirebond between the optoelectronic component and the base substrate is removed.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 29, 2020
    Assignee: REFLEX PHOTONICS INC.
    Inventor: David Robert Cameron Rolston
  • Patent number: 10872847
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 10873015
    Abstract: A light emitting device includes a plurality of light emitting elements and a package. The package includes two metal parts on which the plurality of light emitting elements are disposed, and a resin body securing the two metal parts. The resin body has four sides and four connecting parts alternately connected to one another in a top view. Two subsequent sides are perpendicular to each other. Each of the two metal parts includes a die-pad on which one or more of the plurality of light emitting elements are disposed, and two extending portions extending from the die-pad. An end portion of each of the two extending portions is extended laterally outward from a respective one of the connecting parts of the resin body, and the end portion of each of the two extending portions is located inward of virtual extension lines of corresponding two sides of the resin body.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 22, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Hiroaki Ukawa, Ryo Iwasa
  • Patent number: 10841679
    Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Liang Hsiao, Yu-Hsuan Tsai, Pu Shan Huang, Ching-Han Huang, Lu-Ming Lai
  • Patent number: 10822226
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 3, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Patent number: 10788701
    Abstract: A light emitting device package is disclosed. The light emitting device package includes a body, first and second reflection cups spaced apart from each other in a top surface of the body, a first connection pad disposed in the top surface of the body, spaced apart from the first and second reflection cups, a first light emitting diode mounted in the first reflection cup, a second light emitting diode mounted in the second reflection cup, and a partition wall disposed between the first reflection cup and the second reflection cup, the partition wall extended from the top surface of the body upwardly.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: September 29, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Bong Kul Min
  • Patent number: 10790427
    Abstract: Disclosed are a lens for a light-emitting device usable in a display apparatus or a lighting apparatus, and a method of manufacturing a light-emitting device package. The lens may include a lens body including a light-receiving portion provided in a lower surface of the lens body, a light-emitting portion provided on an upper surface of the lens body, and a recess provided at a center of the upper surface of the lens body, and a flat portion provided in a horizontal shape on a bottom surface of the recess perpendicularly to a main emission line of light emitted from a light-emitting device to emit at least a part of light received through the light-receiving portion, upward. A diameter of the flat portion may be 1/100 to 1/10 of an inlet diameter of the light-receiving portion.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 29, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Seung Hyun Oh, Yun Geon Cho, Young Mi Na, Byeong Cheol Shim, Bo Gyun Kim, Jong Kyung Lee
  • Patent number: 10763286
    Abstract: The present technology relates to a semiconductor device providing an image sensor package capable of coping with an increase in the number of I/Os of an image sensor, a manufacturing method thereof, and an electronic apparatus. The semiconductor device includes an image sensor, a glass substrate, a wiring layer, and external terminals. In the image sensor, photoelectric conversion elements are formed on a semiconductor substrate. The glass substrate is arranged on a first main surface side of the image sensor. The wiring layer is formed on a second main surface side opposite to the first main surface. Each of the external terminals outputs a signal of the image sensor. Metal wiring of the wiring layer extends to an outer peripheral portion of the image sensor and is connected to the external terminals. The present technology can be applied to, for example, an image sensor package and the like.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 1, 2020
    Assignee: Sony Corporation
    Inventors: Susumu Hogyoku, Shun Mitarai, Shusaku Yanagawa
  • Patent number: 10756027
    Abstract: A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.
    Type: Grant
    Filed: March 31, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Zhibiao Zhou
  • Patent number: 10748829
    Abstract: An encapsulation structure to protect an image sensor chip at all times during manufacture and use includes a printed circuit board, an image sensor chip, a supporting portion, a protecting film and a package portion. The image sensor chip is mounted on the printed circuit board and the supporting portion is mounted on the printed circuit board to surround the image sensor chip. The package portion is entirely opaque and is formed on the printed circuit board, the package portion encloses side wall of the supporting portion and the protecting film, and portion of surface of the protecting sheet away from the image sensor chip.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN CO.LTD.
    Inventors: Chia-Wei Chen, Shin-Wen Chen
  • Patent number: 10745269
    Abstract: A package includes a support structure having an electrically insulating material, a microelectromechanical system (MEMS) component, a cover structure having an electrically insulating material and mounted on the support structure for at least partially covering the MEMS component, and an electronic component embedded in one of the support structure and the cover structure. At least one of the support structure and the cover structure has or provides an electrically conductive contact structure.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: August 18, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Nick Renaud-Bezot, Bernhard Reitmaier
  • Patent number: 10734351
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Patent number: 10720753
    Abstract: A mount connects a light emitting device, such as a laser diode assembly, to an optical bench. The mount may include a thermoelectrical module coupled to a sub-element of a heat exchanger extending through an opening formed in the optical bench. The thermoelectrical module acts as a heat sink to draw heat outwardly from the laser diode and cool the same. The heat sink enables the laser diode to transmit heat thereto such that substantially all of the heat generated by the laser diode sinks to the heat exchanger. As such, the laser diode transfers virtually no heat to the optical bench so the optical bench is free of deflections or distortions resultant from the heat generated during generation of the laser beam.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: David B. Belley, Erik J. Spahr
  • Patent number: 10714528
    Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 14, 2020
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Shih-Kuang Chen, Chin-Ching Huang, Chia-Ming Cheng
  • Patent number: 10712197
    Abstract: An optical device package is disclosed. The optical device package includes a substrate that passes light at an optical wavelength. The optical device package also includes an optical device assembly that is mounted to the substrate. The optical device assembly comprises an optical device die. The optical device die has a first surface that is mounted to and facing the substrate and a second surface that is opposite the first surface. The optical device package further includes a molding compound that is disposed at least partially over the second surface of the integrated device die.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 14, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: David Frank Bolognia, Camille Louis Huin, Brian Hall
  • Patent number: 10707161
    Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 7, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Hua Hong Tan, Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto
  • Patent number: 10692719
    Abstract: A nanowire includes an electrically conductive catalyst nanoparticle first portion, a semiconductor wire second portion, a first dielectric shell around the first portion, and a second dielectric shell or functionalization around the second portion. A material of the second dielectric shell or functionalization is different from a material of the first shell.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: June 23, 2020
    Assignee: AligND Systems AB
    Inventors: Umear Naseem, Klaus Kunze
  • Patent number: 10672428
    Abstract: A method to record data in a solid substrate comprises modulating a polarization angle of a coherent optical pulsetrain, and, while the polarization angle is being modulated, focusing the coherent optical pulsetrain on a locus moving through the solid substrate at a relative velocity. Here the relative velocity, a width of the locus in a direction of the relative velocity, and a rate of modulation of the polarization angle are such that the substrate receives within the width of the locus two or more pulses of the optical pulsetrain differing in polarization angle. In this manner, the two or more pulses record, in different portions of the substrate within the width of the locus, two or more different symbols.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 2, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Richard John Black, Patrick Neil Anderson, Rokas Drevinskas, Austin Nicholas Donnelly, Hugh David Paul Williams
  • Patent number: 10629518
    Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Vikas Shilimkar, Ramanujam Srinidhi Embar
  • Patent number: 10620764
    Abstract: The present disclosure relates to a color filter substrate, a fabrication method thereof, and a display panel. The color filter substrate includes: a substrate including a first surface and a second surface opposite to each other; a color filter film disposed on the first surface of the substrate; and a force sensitive film disposed on the second surface of the substrate. Further, the force sensitive film is configured to act as a conductor when no pressure is applied and as a non-conductor when under pressure.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dongling Sun, Xiaobin Yin, Zhengwei Zhu, Wencheng Hu
  • Patent number: 10624204
    Abstract: An optical module includes a conductor plate including a first through hole, a signal lead terminal fixed to the first through hole, and a wiring circuit board. The wiring circuit board includes a signal strip conductor member and a land on a first surface and a ground conductor layer and a second through hole on a second surface, the land surrounds the second through hole and is in contact with the signal strip conductor member, the signal lead terminal and the land are physically connected to each other through a solder and thus the signal lead terminal and the signal strip conductor member are electrically connected to each other, and at least a part of the land spreads outwardly, in a plan view, from not only a portion in contact with the signal strip conductor member but also an outer edge of the first through hole.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 14, 2020
    Assignee: Lumentum Japan, Inc.
    Inventors: Daisuke Noguchi, Hiroshi Yamamoto
  • Patent number: 10617397
    Abstract: A sample capture and transport unit comprises a housing defining a substrate chamber for containing a sample-capture substrate. The housing comprises at least a first part and a second part which are movable relative to one another ? i) from a first closed configuration in which the substrate chamber is inaccessible; ? ii) to a first open configuration in which access to the substrate chamber is enabled to allow capturing of a skin-print on a sample-capture substrate contained within the substrate chamber; and subsequently ? iii) into a second closed configuration in which the substrate chamber is again inaccessible. The unit further comprises a retaining mechanism for retaining it in the second closed configuration. The retaining mechanism is disablable to permit movement of the unit out of the second closed configuration. A sample can be obtained at a first location, secured for transport and analysed at a second location.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 14, 2020
    Assignee: INTELLIGENT FINGERPRINTING LIMITED
    Inventors: Mark Hudson, Nicholas Earl, Daniel Peterson Godfrey, John Dunton