With Housing Or Encapsulation Patents (Class 257/433)
  • Patent number: 10763286
    Abstract: The present technology relates to a semiconductor device providing an image sensor package capable of coping with an increase in the number of I/Os of an image sensor, a manufacturing method thereof, and an electronic apparatus. The semiconductor device includes an image sensor, a glass substrate, a wiring layer, and external terminals. In the image sensor, photoelectric conversion elements are formed on a semiconductor substrate. The glass substrate is arranged on a first main surface side of the image sensor. The wiring layer is formed on a second main surface side opposite to the first main surface. Each of the external terminals outputs a signal of the image sensor. Metal wiring of the wiring layer extends to an outer peripheral portion of the image sensor and is connected to the external terminals. The present technology can be applied to, for example, an image sensor package and the like.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 1, 2020
    Assignee: Sony Corporation
    Inventors: Susumu Hogyoku, Shun Mitarai, Shusaku Yanagawa
  • Patent number: 10756027
    Abstract: A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.
    Type: Grant
    Filed: March 31, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Zhibiao Zhou
  • Patent number: 10748829
    Abstract: An encapsulation structure to protect an image sensor chip at all times during manufacture and use includes a printed circuit board, an image sensor chip, a supporting portion, a protecting film and a package portion. The image sensor chip is mounted on the printed circuit board and the supporting portion is mounted on the printed circuit board to surround the image sensor chip. The package portion is entirely opaque and is formed on the printed circuit board, the package portion encloses side wall of the supporting portion and the protecting film, and portion of surface of the protecting sheet away from the image sensor chip.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN CO.LTD.
    Inventors: Chia-Wei Chen, Shin-Wen Chen
  • Patent number: 10745269
    Abstract: A package includes a support structure having an electrically insulating material, a microelectromechanical system (MEMS) component, a cover structure having an electrically insulating material and mounted on the support structure for at least partially covering the MEMS component, and an electronic component embedded in one of the support structure and the cover structure. At least one of the support structure and the cover structure has or provides an electrically conductive contact structure.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: August 18, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Nick Renaud-Bezot, Bernhard Reitmaier
  • Patent number: 10734351
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Patent number: 10720753
    Abstract: A mount connects a light emitting device, such as a laser diode assembly, to an optical bench. The mount may include a thermoelectrical module coupled to a sub-element of a heat exchanger extending through an opening formed in the optical bench. The thermoelectrical module acts as a heat sink to draw heat outwardly from the laser diode and cool the same. The heat sink enables the laser diode to transmit heat thereto such that substantially all of the heat generated by the laser diode sinks to the heat exchanger. As such, the laser diode transfers virtually no heat to the optical bench so the optical bench is free of deflections or distortions resultant from the heat generated during generation of the laser beam.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: David B. Belley, Erik J. Spahr
  • Patent number: 10714528
    Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 14, 2020
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Shih-Kuang Chen, Chin-Ching Huang, Chia-Ming Cheng
  • Patent number: 10712197
    Abstract: An optical device package is disclosed. The optical device package includes a substrate that passes light at an optical wavelength. The optical device package also includes an optical device assembly that is mounted to the substrate. The optical device assembly comprises an optical device die. The optical device die has a first surface that is mounted to and facing the substrate and a second surface that is opposite the first surface. The optical device package further includes a molding compound that is disposed at least partially over the second surface of the integrated device die.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 14, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: David Frank Bolognia, Camille Louis Huin, Brian Hall
  • Patent number: 10707161
    Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 7, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Hua Hong Tan, Wilson Poh Leng Ong, Kriangsak Sae Le, Saravuth Sirinorakul, Somsak Phukronghin, Paweena Phatto
  • Patent number: 10692719
    Abstract: A nanowire includes an electrically conductive catalyst nanoparticle first portion, a semiconductor wire second portion, a first dielectric shell around the first portion, and a second dielectric shell or functionalization around the second portion. A material of the second dielectric shell or functionalization is different from a material of the first shell.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: June 23, 2020
    Assignee: AligND Systems AB
    Inventors: Umear Naseem, Klaus Kunze
  • Patent number: 10672428
    Abstract: A method to record data in a solid substrate comprises modulating a polarization angle of a coherent optical pulsetrain, and, while the polarization angle is being modulated, focusing the coherent optical pulsetrain on a locus moving through the solid substrate at a relative velocity. Here the relative velocity, a width of the locus in a direction of the relative velocity, and a rate of modulation of the polarization angle are such that the substrate receives within the width of the locus two or more pulses of the optical pulsetrain differing in polarization angle. In this manner, the two or more pulses record, in different portions of the substrate within the width of the locus, two or more different symbols.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 2, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Richard John Black, Patrick Neil Anderson, Rokas Drevinskas, Austin Nicholas Donnelly, Hugh David Paul Williams
  • Patent number: 10629518
    Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Vikas Shilimkar, Ramanujam Srinidhi Embar
  • Patent number: 10624204
    Abstract: An optical module includes a conductor plate including a first through hole, a signal lead terminal fixed to the first through hole, and a wiring circuit board. The wiring circuit board includes a signal strip conductor member and a land on a first surface and a ground conductor layer and a second through hole on a second surface, the land surrounds the second through hole and is in contact with the signal strip conductor member, the signal lead terminal and the land are physically connected to each other through a solder and thus the signal lead terminal and the signal strip conductor member are electrically connected to each other, and at least a part of the land spreads outwardly, in a plan view, from not only a portion in contact with the signal strip conductor member but also an outer edge of the first through hole.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 14, 2020
    Assignee: Lumentum Japan, Inc.
    Inventors: Daisuke Noguchi, Hiroshi Yamamoto
  • Patent number: 10617397
    Abstract: A sample capture and transport unit comprises a housing defining a substrate chamber for containing a sample-capture substrate. The housing comprises at least a first part and a second part which are movable relative to one another ? i) from a first closed configuration in which the substrate chamber is inaccessible; ? ii) to a first open configuration in which access to the substrate chamber is enabled to allow capturing of a skin-print on a sample-capture substrate contained within the substrate chamber; and subsequently ? iii) into a second closed configuration in which the substrate chamber is again inaccessible. The unit further comprises a retaining mechanism for retaining it in the second closed configuration. The retaining mechanism is disablable to permit movement of the unit out of the second closed configuration. A sample can be obtained at a first location, secured for transport and analysed at a second location.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 14, 2020
    Assignee: INTELLIGENT FINGERPRINTING LIMITED
    Inventors: Mark Hudson, Nicholas Earl, Daniel Peterson Godfrey, John Dunton
  • Patent number: 10623613
    Abstract: A camera module with excellent strength is provided. A camera module includes a housing to which a lens unit is attached and a substrate having a certain positional relationship with the lens unit and supported by the housing, where the housing includes an adhesive agent pool provided to a first main plane of the substrate with a certain opposing space and an open end of an adhesive agent path including the opposing space that is provided to a side of a second main plane of the substrate.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SMK Corporation
    Inventors: Taku Akaiwa, Nobuyuki Mano
  • Patent number: 10620764
    Abstract: The present disclosure relates to a color filter substrate, a fabrication method thereof, and a display panel. The color filter substrate includes: a substrate including a first surface and a second surface opposite to each other; a color filter film disposed on the first surface of the substrate; and a force sensitive film disposed on the second surface of the substrate. Further, the force sensitive film is configured to act as a conductor when no pressure is applied and as a non-conductor when under pressure.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dongling Sun, Xiaobin Yin, Zhengwei Zhu, Wencheng Hu
  • Patent number: 10497731
    Abstract: A photoelectric conversion device includes a semiconductor substrate having a photoelectric conversion unit, a magnetic layer arranged over an opposite side to a light-receiving face of the semiconductor substrate, and an infrared ray absorbing layer arranged between the semiconductor substrate and the magnetic layer.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 3, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yuichi Kazue, Takahiro Hachisu
  • Patent number: 10490583
    Abstract: A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 26, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Fangyuan Hong
  • Patent number: 10459241
    Abstract: Imaging apparatus and methods using diffraction-based illumination are disclosed. An example apparatus includes a diffraction grating to redirect light from a light source toward a sample to thereby illuminate the sample. The example apparatus also includes an image sensor to detect a diffraction pattern created by the illuminated sample.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 29, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Charles M Santori, Alexander Govyadinov
  • Patent number: 10461116
    Abstract: The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: October 29, 2019
    Assignee: NINGBO SUNNY OPOTECH CO., LTD.
    Inventors: Mingzhu Wang, Bojie Zhao, Takehiko Tanaka, Zhenyu Chen, Heng Jiang, Nan Guo
  • Patent number: 10418294
    Abstract: A described example includes: a die with an active surface; a cap mounted over a portion of the active surface of the die; and mold compound covering the cap and covering portions of the die, the cap excluding the mold compound from contact with the portion of the active surface of the die.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Laura May Antoinette Dela Paz Clemente, Jerry Gomez Cayabyab
  • Patent number: 10378736
    Abstract: An LED bracket, LED bracket array, LED device and LED display screen are disclosed. The LED bracket includes a PCB circuit substrate and an insulating material. The PCB circuit substrate includes at least two electrically insulated electrode regions. Each electrode region includes a top electrode region, a side electrode region and a bottom electrode region. The side electrode region connects the top electrode region and the bottom electrode region into an integrated structure. The side electrode region is a side surface sunk from outside to an inner part of the PCB circuit substrate. The insulating material is filled in the side electrode region. An upper end surface and a lower end surface of the insulating material do not exceed an upper surface and a lower surface of the PCB circuit substrate. A thickness of the insulating material is less than a thickness of the PCB circuit substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Foshan NationStar Optoelectronics Co., Ltd.
    Inventors: Chuanbiao Liu, Feng Gu, Yuanbin Lin, Xiangling Luo, Xiaofeng Liu, Xi Zheng, Yan Liu
  • Patent number: 10347774
    Abstract: A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 9, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Noriyuki Kishi, Tatsuhiro Koizumi, Hiroyuki Shiraki, Mitsuru Tamashiro, Masaya Yamamoto
  • Patent number: 10304815
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10298818
    Abstract: A camera for a vision system for a vehicle includes an imager chip having an at least partially light transmitting substrate having a photosensor array disposed at a second surface of the at least partially light transmitting substrate so as to sense light that passes through the at least partially light transmitting substrate. The imager chip includes electrically conductive pads disposed at the second surface of the at least partially light transmitting substrate. A circuit element includes circuitry disposed at least at a third surface thereof. The imager chip is mounted at the circuit element with the second surface of the at least partially light transmitting substrate opposing the third surface of the circuit element. Electrical connection between the electrically conductive pads and the circuitry of the circuit element is made when mounting the imager chip at the circuit element.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 21, 2019
    Assignee: MAGNA ELECTRONICS INC.
    Inventor: Christopher L. Van Dan Elzen
  • Patent number: 10288985
    Abstract: An imaging device having a lens group; a lens barrel holding the lens group; a base member holding the lens barrel; an imaging element; a fixed plate arranged facing at least part of the base member in a state in which the imaging element is fixed; and a pressing member for attaching, to the base member, the fixed plate in a state in which the fixed plate is temporarily fixed to the base member in a state in which fixed plate is movable in a direction intersecting the axial line of the lens group, relative to the base member.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 14, 2019
    Assignee: Nidec Copal Corporation
    Inventors: Yuta Nakamura, Ryo Kikuta
  • Patent number: 10276506
    Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10269852
    Abstract: A device includes a first integrated circuit containing a photodiode and a first metal interconnect structure connected to the photodiode, and a second integrated circuit containing a transistor and a second metal interconnect structure connected to the transistor. The first integrated circuit and the second integrated circuit are connected together through the first metal interconnect structure and the second metal interconnect structure. Since no transistor is present around the photodiode, the photodiode has an increased photosensitive area and an improved fill factor, resulting in an increase of the quantum efficiency, higher integration and lower consumption of the image sensor.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Jerry Liu, Phil Wu, Herb He Huang
  • Patent number: 10217879
    Abstract: The present invention provides an optical semiconductor device in which damage of a lens when being mounted and mounting displacement due to suction failures of a chip can be suppressed. An optical semiconductor device according to an embodiment includes: a semiconductor substrate having a first surface and a second surface facing the first surface; an electrode formed over the first surface of the semiconductor substrate; an optical element that is electrically coupled to the electrode and is formed in the semiconductor substrate; and a lens arranged on the second surface side of the optical element. A concave part is formed in the second surface of the semiconductor substrate, and the lens is arranged at the bottom of the concave part. A top part on the second surface side of the lens is located on the first surface side relative to the second surface located around the concave part.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshito Taniguchi
  • Patent number: 10211249
    Abstract: An x-ray detector includes a substrate including an electrically conductive connection between a read-out contact in the region of the top side of the substrate and an input of a pre-amplifier in an active layer of an integrated circuit. A first electrically conductive connection is provided between the read-out contact and a second electrically conductive connection. A surface of a first light protection is relatively larger than a surface of a light-permeable region of the first light protection. The second electrically conductive connection is provided within a second projection of the surface of the light-permeable region along the surface normal and below the second light protection. A third electrically conductive connection between the second electrically conductive connection and the pre-amplifier is provided below the second light protection. The input of the pre-amplifier is protected against direct incidence of light.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 19, 2019
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Martin Groepl, Edgar Goederer, Thomas Suttorp
  • Patent number: 10197750
    Abstract: A light guiding structure is provided. The structure includes an anodized aluminum oxide (AAO) layer and a fluoropolymer layer located immediately adjacent to a surface of the AAO layer. Light propagates through the AAO layer in a direction substantially parallel to the fluoropolymer layer. An optoelectronic device can be coupled to a surface of the AAO layer, and emit/sense light propagating through the AAO layer. Solutions for fabricating the light guiding structure are also described.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10183858
    Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Albert Wan, Yu-Sheng Hsieh, Chao-Wen Shih, Shou Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10177098
    Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Patent number: 10170440
    Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad, and a second bonding pad on a top surface of the stacking structure, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 ?m; a carrier comprising a connecting surface; a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and a conductive connecting layer comprising a current conductive area between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 1, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
  • Patent number: 10157274
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10156717
    Abstract: In an electro-optical device, light is incident on a mirror by penetrating a cover, and the light reflected by the mirror is emitted by penetrating the cover. Here, the cover includes a first light-transmitting plate and a second light-transmitting plate facing the first light-transmitting plate, and a gap which is open toward both sides in a first direction is provided between the first light-transmitting plate and the second light-transmitting plate due to a spacer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 18, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yasuo Yamasaki
  • Patent number: 10153235
    Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Kwon Jung, Bang Chul Ko, Chul Choi, Jung Hyun Cho, Joo Hwan Jung, Yong Ho Baek, Seung Eun Lee
  • Patent number: 10141286
    Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Il Lee, Cha-Jea Jo, Ji-Hwang Kim
  • Patent number: 10134961
    Abstract: Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In one aspect, a method of providing a submount based light emitter component can include providing a ceramic based submount, providing at least one light emitter chip on the submount, providing at least one electrical contact on a portion of the submount, and providing a non-ceramic based reflector cavity on a portion of the submount.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 20, 2018
    Assignee: Cree, Inc.
    Inventors: Jesse Colin Reiherzer, Christopher P. Hussell
  • Patent number: 10134957
    Abstract: A surface-mountable optoelectronic semiconductor component is specified. The surface-mountable optoelectronic semiconductor component includes an optoelectronic semiconductor chip, a radiation-transmissive growth substrate, a housing body and an electrically conductive connection. The housing body is arranged at least in places between a side surface of the growth substrate and the electrically conductive connection. The housing body completely covers all of the side surfaces of the growth substrate, and the housing body has, on a surface facing away from the side surface of the growth substrate, traces of material removal or traces of a form tool.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: November 20, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Norwin von Malm
  • Patent number: 10129452
    Abstract: A camera module and an array camera module based on an integral packing process are disclosed. The camera module or each of the camera module units of the array camera module includes a circuit board, an integral base, a photosensitive element operatively connected to the circuit board, a lens, a light filter holder installed at the integral base and a light filter installed at the light filter holder. The light filter is not required to be directly installed to the integral base, so that the light filter is protected and the requiring area of the light filter is reduced.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: November 13, 2018
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Nan Guo, Takehiko Tanaka
  • Patent number: 10083939
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10084135
    Abstract: An illumination device includes a substrate, a light emitting structure, a sealant, and a laminating board is provided. The light emitting structure includes a first electrode layer, a light emitting layer and a second electrode layer stacked on the substrate sequentially. The sealant covers the light emitting structure. The laminating board is attached to the substrate. The sealant is located between the laminating board and the substrate. The laminating board includes a carrier body, a metal layer and a plurality of pads. The metal layer is exposed at a first surface of the carrier body, is in contact with the sealant and shields an area of the light emitting layer of the light emitting structure. The pads are exposed at the first surface of the carrier body and electrically connected to the first electrode layer and the second electrode layer. The metal layer is electrically isolated from the pads.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 25, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Hsuan-Yu Lin, Hsin-Chu Chen, Wen-Hong Liu, Chao-Feng Sung, Chun-Ting Liu, Je-Ping Hu, Wen-Yung Yeh
  • Patent number: 10079198
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 18, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
  • Patent number: 10078007
    Abstract: An infrared sensor includes an infrared detecting device, a lens, a member, a gap and a spacer. The lens is disposed above the infrared detecting device. The member forms an external surface and includes a first opening having a maximum internal diameter. The gap is disposed between the member and the lens. The spacer is disposed between the member and the lens so as to form the gap, and that is directly contact with lens. The spacer has a circular inner periphery, in planar view, which has a larger internal diameter than the maximum internal diameter of the first opening of the member.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 18, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takafumi Okudo, Takahiro Miyatake, Yoshiharu Sanagawa, Masao Kirihara, Yoichi Nishijima, Takanori Aketa, Ryo Tomoida
  • Patent number: 10060820
    Abstract: Suspending a microelectromechanical system (MEMS) pressure sensing element inside a cavity using spring-like corrugations or serpentine crenellations, reduces thermally-mismatched mechanical stress on the sensing element. Overlaying the spring-like structures and the sensing element with a gel further reduces thermally-mismatched stress and vibrational dynamic stress.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Shiuh-Hui Steven Chen, Jen-Huang Albert Chiou, Robert C. Kosberg, Daniel Roy Empen
  • Patent number: 10020343
    Abstract: Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 10, 2018
    Assignee: FLIR Systems, Inc.
    Inventors: Edward K. Huang, Andrew D. Hood, Bryan Gall, Paula Heu, Richard E. Bornfreund
  • Patent number: 9991621
    Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 5, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Konrad Wagner, J├╝rgen Holz
  • Patent number: 9972729
    Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 15, 2018
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Patent number: 9955055
    Abstract: An array imaging module includes at least two optical lenses and a molded photosensitive assembly, wherein the molded photosensitive assembly includes at least two photosensitive units, a circuit board that electrically couples to the photosensitive units, and a molded base having at least two optical windows. The molded base is integrally coupled at the circuit board at a peripheral portion thereof, wherein the photosensitive units are aligned with the optical windows respectively. The optical lenses are located along two photosensitive paths of the photosensitive units respectively, such that each of the optical windows forms a light channel through the corresponding photosensitive unit and the corresponding optical lens.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 24, 2018
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Takehiko Tanaka, Nan Guo, Zhen Huang, Duanliang Cheng, Liang Ding, Feifan Chen, Heng Jiang