Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

Abstract: A method for manufacturing an optical-semiconductor device, including forming a plurality of first and second electrically conductive members that are disposed separately from each other on a support substrate; providing a base member formed from a light blocking resin between the first and second electrically conductive members; mounting an optical-semiconductor element on the first and/or second electrically conductive member; covering the optical-semiconductor element by a sealing member formed from a translucent resin; and obtaining individual optical-semiconductor devices after removing the support substrate.

Abstract: An optical module includes a semiconductor optical device in which an active layer located at one side, an electrode located at the same side, and a mirror that reflects light toward the side opposite the electrode are monolithically integrated, a sub-mount having one surface on which a first wiring pattern is formed, a substrate in which an optical waveguide and a grating coupler are formed in a surface layer of the substrate, a spacer having an upper surface on which a second wiring pattern is formed, and a wire. The sub-mount is mounted on the spacer. The first wiring pattern on the sub-mount faces part of the second wiring pattern on the spacer and is electrically connected thereto. The second wiring pattern on the spacer includes a pad being disposed in a region exposed from the sub-mount and being bonded to the wire.

Abstract: A configurable LED lighting system and its method of operation are disclosed. A lighting system or apparatus includes a string of LEDs, wherein specific LEDs are operable to emit different colors of light. The string includes a plurality of series-connected color segments. A shunt segment includes additional LEDs. The LED shunt segment is connected in parallel with at least one of the color segments. A controller is connected to the LED shunt segment to selectively balance drive current between the LED shunt segment and the color segment to which it is connected in parallel so that a color temperature of light is controllable by a processor. The diverted power still produces light and power is not wasted. The controller can use a polynomial equation or a look-up table to calculate color output values.

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first integrated circuit chip including light-emitting diodes; b) bonding a second integrated chip to a first surface of the first chip; c) decreasing the thickness of the first chip on the side opposite to the first surface to form a second surface opposite to the first surface; d) bonding, to the second surface, a cap including a silicon wafer provided with recesses opposite the light-emitting diodes; e) decreasing the thickness of the second chip; f) decreasing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) sawing the structure obtained at step f) into a plurality of separate optoelectronic devices.

Abstract: A surface mount high-frequency circuit is configured such that a plurality of ground pads 41 and a plurality of external connection ground conductors 51 are discretely disposed to surround a signal line pad 42 and an external connection signal line conductor 52, and a plurality of interlayer connection ground conductors 31 and that a plurality of columnar ground conductors 12 are discretely disposed to surround an interlayer connection signal line conductor 32. Thus, it is possible to suppress radiation of an unnecessary signal to the outside using a simple production process that is completed by only a wafer process without separately preparing a component such as a shield cover case.

Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.

Abstract: The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

Abstract: Provided are methods of manufacturing a substrate for an OED and an OED. According to the methods of manufacturing a substrate for forming an OED such as an OLED and an OED, a substrate for forming a device having excellent light extraction efficiency and improved reliability by preventing penetration of moisture or air into the device, or device using the same may be provided.

Abstract: Embodiments of the present disclosure are directed towards apparatuses, systems, and methods for die attach coatings for semiconductor packages. In one embodiment, a die may be coupled with a substrate by a die attach and a coating may be applied to an edge of the die attach.

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Abstract: A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

Abstract: A semiconductor package comprises a top package and a bottom package with a plurality of fan-out interconnect structures. A plurality of inter-package connectors are formed inside a gap between the top package and the bottom package. A conductive protection layer is formed over the semiconductor package, wherein the conductive protection layer seals the gap around its perimeter, wherein the conductive protection layer covers an upper surface and a side wall of the top package, and wherein the conductive protection layer covers portions of an upper surface of the bottom package that extend beyond a boundary of the top package and a top portion of a side wall of the bottom package.

Abstract: A compact optical system is provided. The system includes a first optical module, a first substrate, a second optical module, and a second substrate. The first optical module is utilized to modulate a laser beam. The first substrate supports the first optical module, and the first substrate defines a first optical via such that the laser beam can pass through the first substrate through the first optical via. The second optical module receives the laser beam from the first optical via for modulating the laser beam. The second substrate is disposed parallel to the first substrate and away from the first substrate with a first predetermined distance and utilized to support the second optical module. An ultrafast laser thereof is further provided.

Abstract: Vision systems including a swappable camera and methods of making and using the swappable camera are disclosed. The swappable camera can include an alignment indicator storing alignment data representative of an array-housing alignment of a sensor array relative to a camera housing. The swappable camera can have a desired sensor array position. A region of interest that is concentric with the desired sensor array position can be determined using the alignment data and an image can be acquired using only pixels of the sensor array that are located within the region of interest.

Abstract: Disclosed is a solid-state imaging device including: a solid-state imaging element which outputs an image signal according to an amount of light sensed on a light sensing surface; a semiconductor element which performs signal processing with respect to the image signal output from the solid-state imaging element; and a substrate which is electrically connected to the solid-state imaging element and the semiconductor element, in which the semiconductor element is sealed by a molding resin in a state of being accommodated in an accommodation area which is provided on the substrate, and in which the solid-state imaging element is layered on the semiconductor element via the molding resin.

Abstract: A sensor package that includes a substrate with opposing first and second surfaces. A plurality of photo detectors are formed on or under the first surface and configured to generate one or more signals in response to light incident on the first surface. A plurality of contact pads are formed at the first surface and are electrically coupled to the plurality of photo detectors. A plurality of holes are each formed into the second surface and extending through the substrate to one of the contact pads. Conductive leads each extend from one of the contact pads, through one of the plurality of holes, and along the second surface. The conductive leads are insulated from the substrate. One or more trenches are formed into a periphery portion of the substrate each extending from the second surface to the first surface. Insulation material covers sidewalls of the one or more trenches.

Abstract: Embodiments include devices and methods of their manufacture. A device embodiment includes a package housing, at least one electronic circuit (e.g., a sensor circuit), a first material, and a second material. The package housing includes a cavity that is partially defined by a cavity bottom surface, and the cavity bottom surface includes a mounting area and a non-mounting area. The at least one electronic circuit is attached to the cavity bottom surface over the mounting area. The first material has a relatively high, first modulus of elasticity, and covers the non-mounting area. The second material has a relatively low, second modulus of elasticity, and is disposed over the first material within the cavity.

Abstract: Light emitting devices, systems, and methods are disclosed. In one embodiment a light emitting device can include an emission area having one or more light emitting diodes (LEDs) mounted over an irregularly shaped mounting area. The light emitting device can further include a retention material disposed about the emission area. The retention material can also be irregularly shaped, and can be dispensed. Light emitting device can include more than one emission area per device.

Abstract: A solid-state imaging device includes a supporting substrate that includes a concave portion, a solid-state imaging chip that is bonded on the supporting substrate so as to seal the concave portion in a view-angle region, a stress film that is formed on the surface of the solid-state imaging chip, and an imaging surface curved toward the concave portion at least in the view-angle region.

Abstract: An image pickup module includes: a wiring board including a first main surface on which chip electrodes are disposed and a second main surface on which the cable electrodes connected respectively to the chip electrodes via respective through wirings are disposed; an image pickup device chip including external electrodes bonded respectively to the chip electrodes; and a cable including conductive wires bonded respectively to the cable electrodes, in which all of the cable electrodes are disposed in a region not facing a region where the chip electrodes are disposed.

Abstract: A photoreception device includes: a substrate; a photoreceptor element including a photoreceptor portion upon an upper surface thereof and a lower surface thereof is mounted upon the substrate; and an insulating resin mass that contains a flat upper surface and an opening that exposes the photoreceptor portion of the photoreceptor element, that is formed upon the substrate to be thicker than thickness of the photoreceptor element, and that adheres closely against side surfaces of the photoreceptor element, the side surfaces surrounding the photoreceptor element. The insulating resin mass contains a step portion that is provided to a height between the flat upper surface thereof and the upper surface of the photoreceptor portion; and the step portion extends parallel to at least one pair of mutually opposed side surfaces of the photoreceptor element, at a periphery of the opening.

Abstract: A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength.

Abstract: The present invention relates to integrated circuit packaging and methods of manufacturing these. In particular, but not exclusively the present invention relates to improvements in the suppression of spurious wave modes within cavity packages in which are mounted circuits operating at high frequencies, for example Monolithic Microwave Integrated Circuits (MMIC's).

Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.

Abstract: Thermal interface material handing is described for thermal control of an electronic component under test. In one example, a thermal control unit is adapted to control the temperature of at least a portion of an electronic component during testing. A pedestal between the thermal control unit and the electronic component conducts heat from the electronic component to the thermal head. A conduit extends through a portion of the pedestal, to permit the flow of a liquid thermal interface material from an external source to a space between the pedestal and the electronic component. The liquid thermal interface material improves heat conduction between the electronic component and the pedestal. An elastomeric seal between the electronic device and the pedestal constrains the thermal interface fluid within the space between the electronic component and the pedestal.

Abstract: Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.

Abstract: An embedded component structure includes a wiring board, a component and an encapsulant. The wiring board has a front side, a reverse side opposite to the front side, an opening and an interconnection layer. The opening penetrates the wiring board and connects the front side and the reverse side of the wiring board. The interconnection layer is located on the front side of the wiring board and extends toward the opening. The component includes an active surface, a back side opposite to the active side, and a working area located on the active surface. The active surface is connected to the interconnection layer of the wiring board. The encapsulant is filled inside the opening and covers the component, which makes the working area of the component exposed. Besides, a method of the embedded component structure is also provided.

Abstract: Methods and systems for a reversible top/bottom MEMS package may comprise a base substrate comprising metal traces, an opening through the base substrate, a die coupled to a first surface of the substrate and positioned over the opening, a frame member coupled to the first surface of the substrate wherein the die is positioned interior of the frame member, a cover substrate coupled to the frame member, and conductive plating on the frame member that electrically couples the base substrate to the cover substrate, wherein the conductive plating is exposed. The conductive plating may couple a ground plane in the base substrate to a ground plane in the cover substrate. The conductive plating may be exposed at an outer surface of the frame member and/or at an inner perimeter of the frame member. Conductive vias within the frame member may be coupled to the metal traces in the base substrate.

Abstract: An electronic component mounting package includes a first base including an upper surface and a first through-hole vertically formed; a second base having a second through-hole arranged to be overlapped with the first through-hole in a plan view; a sealing material filling the second through-hole; and a signal terminal that is fixed to the second base to pass through the sealing material and has an upper end portion that protrudes upwardly from the upper surface of the first base. The first base includes a plurality of first metal members and a second metal member, and the second metal member is vertically interposed between the plurality of first metal members. A thermal expansion coefficient of the first metal members is larger than a thermal expansion coefficient of the second base. A thermal conductivity of the second metal member is higher than a thermal conductivity of the first metal members.

Abstract: A semiconductor image sensor module 1 at least includes a semiconductor image sensor chip 2 having a transistor forming region on a first main surface of a semiconductor substrate and having a photoelectric conversion region with a light incident surface formed on a second main surface on the side opposite to the first main surface and an image signal processing chip 3 for processing image signals formed in the semiconductor image sensor chip 2, wherein a plurality of bump electrodes 15a are formed on a first main surface, a plurality of bump electrodes 15b are formed on the image signal processing chip 3, both the chips 2 and 3 are formed to be laminated through heat dissipating means 4 and the plurality of bump electrodes 15a of the semiconductor image sensor chip 2 and the plurality of bump electrodes 15b on the image signal processing chip 3 are electrically connected.

Abstract: A scanning lens molded of resin includes: a lens portion having an elongate shape extending in a main scanning direction and having an optical surface; a slant portion having at least one slant surface slanting relative to the main scanning direction; and an ejector pin mark formed on the slant surface when thrusting out the scanning lens by ejector pins. The ejector pin mark is formed along a slanting direction of the slant surface.

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a carrier substrate disposed on the second substrate; an insulating layer disposed on a surface and a sidewall of the carrier substrate, wherein the insulating layer fills the at least one opening of the second substrate; and a conducting layer disposed on the insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.

Abstract: A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract: A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract: A manufacture method for a surface mounted power LED support comprises providing a wiring board having both sided metal layers. In addition, the method comprises forming a hole. Further, the method comprises setting a metal layer in the surface of the hole. Still further, the method comprises thickening the metal layer of the wiring board. The method also comprises etching the metal layer of the wiring board. Moreover, the method comprises cutting the wiring board to form single support unit. A surface mounted power LED support comprises a both sided wiring board, a hole formed in the wiring board and wiring layers set on the surface of the wiring board.

Abstract: Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Abstract: An integrated fluorescence detector for detecting fluorescent particles is described. An example integrated fluorescence detector comprises a substrate, the substrate comprising an integrated detection element for detecting fluorescence radiation from fluorescent particles upon excitation of the particles with incident excitation radiation. The integrated fluorescence detector also comprises a sensing layer adapted for accommodating fluorescent particles to be sensed. The integrated fluorescence detector further comprises a photonics crystal layer arranged in between the sensing layer and the substrate, the photonics crystal layer comprising an absorption material designed such that the photonics crystal layer is configured for diffracting incident excitation radiation into a lateral direction in which the photonics crystal layer extends for incident excitation radiation having a wavelength within at least 10 nm of the predetermined excitation wavelength.

Abstract: A chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other, the semiconductor chip including an image sensor circuit; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; a bond pad formed on the upper surface, for electrically connecting with the image sensor circuit in the semiconductor chip, wherein the metal heat conductive layer conducts or absorbs heat generated by the semiconductor chip, to thereby reduce temperature of the image sensor circuit in the semiconductor chip and improve the performance of the circuit, wherein the metal heat conductive layer entirely covers the lower surface.

Abstract: A stacked die sensor package includes a die paddle and lead fingers that surround the die paddle. The lead fingers have proximal ends near the die paddle and distal ends spaced from the die paddle. A first semiconductor die is mounted to one side of the die paddle and electrically connected to the lead fingers with first bond wires. A sensor die is mounted to the other side of the die paddle and electrically connected to the lead fingers with sensor bond wires. An encapsulation material covers the first die and the first bond wires, while a gel material and a lid cover the sensor die and the sensor bond wires. The package may also have a second semiconductor die attached on an active surface of the first die and electrically connected one or both of the lead fingers or first die bonding pads with second bond wires.

Abstract: An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage.

Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 ?m or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Abstract: A light sensor and a manufacturing method thereof are disclosed. The light sensor is capable of being coupled to a carry object and includes a sensing chip and a plurality of conductive connecting elements. The sensing chip includes a first surface and a second surface opposite to each other. The sensing chip also includes a sensing unit disposed between the first surface and the second surface and at least partially exposed by a window formed on the second surface. The first surface faces the carry object when the light sensor is coupled to a carry object. The conductive connecting elements are disposed on the first surface and coupled to the sensing unit in order to couple the light sensor to the carry object.

Abstract: A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines, including a frame preparing step of preparing a frame having a plurality of crossing partitions corresponding to the division lines of the wafer, a resin covering step of spreading a resin powder on the wafer and positioning the partitions of the frame in alignment with the division lines, thereby covering with the resin powder the regions of the wafer other than the regions corresponding to the division lines, a masking step of melting and curing the resin powder supplied to the wafer processed by the resin covering step and next removing the frame, thereby masking the regions other than the regions corresponding to the division lines, and an etching step of plasma-etching the wafer processed by the masking step to thereby divide the wafer into the individual devices along the division lines.

Abstract: An image pickup device includes a transparent member, an image pickup element chip including a photodiode, and a fixing member arranged around the image pickup element chip, a space being surrounded by the transparent member, the image pickup element chip, and the fixing member. The image pickup element chip includes a semiconductor substrate including a penetrating electrode penetrating through a first main face of the semiconductor substrate on a side of the transparent member and a second main face of the semiconductor substrate opposite the first main face. In an orthogonal projection with respect to the transparent member, the penetrating electrode is arranged in a fixing area corresponding to the fixing member, and a boundary with an area where the thickness of the semiconductor substrate is smaller than that of the semiconductor substrate in a first area corresponding to the space is arranged within the fixing area.

Abstract: A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines includes preparing a frame having a plurality of crossing partitions corresponding to the division lines of the wafer, spreading a liquid resin on the front side or back side of the wafer and positioning the partitions of the frame in alignment with the division lines of the wafer, thereby covering with the liquid resin the regions on the front side or back side of the wafer other than the regions corresponding to the division lines, curing the liquid resin supplied to the front side or back side of the wafer and next removing the frame, thereby masking the regions other than the regions corresponding to the division lines, and plasma-etching the wafer processed by the masking to thereby divide the wafer into the individual devices along the division lines.

Abstract: The invention relates to a lighting element, wherein at least one organic light-emitting diode is formed at an optically transparent substrate as a layer structure. In the lighting element in accordance with the invention, at least one organic light-emitting diode is formed at an optically transparent substrate as a layer structure. The at least one organic light-emitting diode and the substrate are connected to a circuit board and electric contact elements for the connection of the electrodes of the organic light-emitting diode(s) are present at the surface of the circuit board. The surface of the circuit board facing in the direction of the organic light-emitting diode(s) is provided over its full area with a metallic coating as a permeation barrier. The metallic coating is only breached by electric insulators formed about the contact elements.