With Passive Component (e.g., Resistor, Capacitor, Etc.) Patents (Class 257/516)
  • Patent number: 11837395
    Abstract: An inductor component includes a substantially rectangular parallelepiped device body including a first lateral surface and includes a coil conductor layer formed into a spiral wound more than one turn on a main surface parallel to the first lateral surface inside the device body. In the coil conductor layer, a wiring spacing between two wiring portions adjacent to each other (straight portions) in a first direction from an inner side portion to an outer side portion of the coil conductor layer differs from a wiring spacing of two wiring portions adjacent to each other (curved portions) in a second direction from the inner side portion to the outer side portion of the coil conductor layer, the second direction differing from the first direction.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 5, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Mizukami, Hiromi Miyoshi, Keiichi Yoshinaka
  • Patent number: 11830661
    Abstract: An inductor device includes an 8-shaped inductor and a ring-type wire. The ring-type wire is disposed around an outer side of the 8-shaped inductor. The 8-shaped inductor includes an input terminal and a center-tapped terminal. The input terminal of the 8-shaped inductor is located on a first side of the inductor device, and the center-tapped terminal is located on a second side of the inductor device. The ring-type wire includes an input terminal and a ground terminal. The input terminal of the ring-type wire is located on the first side of the inductor device, and the ground terminal is located on the second side of the inductor device. The input terminal of the ring-type wire is coupled to the input terminal of the 8-shaped inductor.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 28, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ping-Yuan Deng
  • Patent number: 11302773
    Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 12, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Ye Lu, Junjing Bao, Haitao Cheng, Chao Song
  • Patent number: 11127748
    Abstract: A semiconductor device includes a substrate, a first insulating layer, a second insulating layer above the first insulating layer, a void space between the first and second insulating layers, and contact electrodes extending through the first insulating layer, the void space, and the second insulating layer. Each of the contact electrodes includes a first end facing the substrate, a second end opposite to the first end, and a first width portion between the first end and the second end. The first width portion has a width in a second direction parallel to the substrate that is greater than a width of the first end in the second direction and a width of the second end in the second direction. The first width portion is within the void space.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 21, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shizuka Kutsukake, Hiroshi Matsumoto, Hiroto Saito
  • Patent number: 10773381
    Abstract: A device includes communication circuitry configured to receive a message indicating an observation of an agent device. The device further includes a processor coupled to the communication circuitry and a memory. The memory stores instructions that are executable by the processor to cause the processor to perform operations. The operations include accessing a blockchain data structure. The blockchain data structure includes one or more blocks including data descriptive of observations of a plurality of agent devices, where the plurality of agent devices including the agent device. The operations also include determining, based on one or more blocks of the blockchain data structure, a behavior of the agent device. The operations also include determine whether the behavior satisfies a behavior criterion associated with the agent device.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 15, 2020
    Assignee: SKYGRID, LLC
    Inventors: Syed Mohammad Amir Husain, Syed Mohammad Ali, Taylor Schmidt
  • Patent number: 10643887
    Abstract: A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method for manufacturing a TFR structure may include forming a pair of spaced-apart TFR heads formed as self-aligned silicide poly (salicide) structures, depositing a dielectric layer over the salicide TFR heads, patterning and etching a trench extending laterally over at least a portion of each salicide TFR head and exposing a surface of each salicide TFR heads is exposed, and depositing a TFR material into the trench and onto the exposed TFR head surfaces, to thereby form a TFR layer that bridges the pair of spaced-apart TFR heads.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 5, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Yaojian Leng
  • Patent number: 10403970
    Abstract: A chip antenna comprising at least one emitter which extends parallel to a main surface of a semiconductor substrate supporting the chip antenna, wherein the emitter is arranged on an island-like support zone of the semiconductor substrate, the support zone being surrounded by at least one trench which is completely filled with a gas, the trench passing through the entire depth of the semiconductor substrate and being bridged by at least one retaining web which forms a supporting connection between the support zone and the rest of the semiconductor substrate.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 3, 2019
    Assignee: IHP GMBH-INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Ruoyu Wang, Yaoming Sun, Johann Christoph Scheytt, Mehmet Kaynak
  • Patent number: 10340236
    Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chung-Shi Liu, Hao-Yi Tsai
  • Patent number: 10163884
    Abstract: An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Harikrishna Chintarlapalli Reddy, Jonathan Holland, Sajin Mohamad
  • Patent number: 10157910
    Abstract: An example circuit includes: one or more power rails and a tap cell structure. The tap cell structure includes one or more decoupling capacitor cells and one or more tap cells. The one or more tap cells are electrically coupled to the one or more power rails. The one or more decoupling capacitor cells are disposed adjacent to the tap cells and electrically coupled to the one or more power rails.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jin-Wei Xu, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien
  • Patent number: 10103067
    Abstract: A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Gunter Grasshoff, Rico Hueselitz
  • Patent number: 9911665
    Abstract: Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wenhu Liu, Sung Mun Jung, Yi Tat Lim, Ling Wu
  • Patent number: 9893048
    Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9887138
    Abstract: A semiconductor device includes first and second MIS transistors and a dummy element. The first MIS transistor includes a first gate insulating film which includes a first high-k insulating film formed on a first active region and contains an adjusting metal. The second MIS transistor includes a second gate insulating film which includes a second high-k insulating film formed on a second active region and is free of the adjusting metal. The dummy element includes a dummy gate insulating film which includes a dummy high-k insulating film formed on a dummy active region and at least a portion of which is free of the adjusting metal. The first active region is formed in a second conductivity type first well region. The second active region is formed in a first conductivity type second well region. The dummy active region is formed in a second conductivity type third well region.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takayuki Yamada, Hideyuki Arai
  • Patent number: 9842815
    Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chung-Shi Liu, Hao-Yi Tsai
  • Patent number: 9761569
    Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 12, 2017
    Assignee: NSP USA, INC.
    Inventor: Weng F. Yap
  • Patent number: 9748326
    Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 29, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 9704855
    Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: July 11, 2017
    Assignee: CoolStar Technology, Inc.
    Inventors: Shuming Xu, Wenhua Dai
  • Patent number: 9659920
    Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
  • Patent number: 9577029
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for manufacturing the same. The method includes a step hereinafter. A 5-layered dual-dielectric structure is provided on a substrate. The 5-layered dual-dielectric structure includes a bottom metal layer, a first dielectric layer, an intermediate metal layer, a second dielectric layer and a top metal layer in order. The first dielectric layer and the second dielectric layer have different thicknesses.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 21, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Zhi-Biao Zhou, Shao-Hui Wu, Chi-Fa Ku
  • Patent number: 9530783
    Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Sung-Bin Lin, Wen-Chung Chang
  • Patent number: 9515133
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: December 6, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He Huang, Hongtao Ge, Haiting Li
  • Patent number: 9502423
    Abstract: A semiconductor includes a gate line having a first portion in a transistor region and a second portion in a decoupling capacitor region.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventors: Myong Kong, Hyo Jin Baek
  • Patent number: 9490027
    Abstract: An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyun Min Song
  • Patent number: 9484444
    Abstract: A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: November 1, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Koichi Mochizuki, Minoru Kawakami
  • Patent number: 9437653
    Abstract: Embodiments relate to stress sensors and methods of sensing stress. In an embodiment, a stress sensor comprises a vertical resistor. The vertical resistor can comprise, for example, an n-type resistor and can have various operating modes. The various operating modes can depend on a coupling configuration of terminals of the resistor and can provide varying piezo-coefficients with very similar temperature coefficients of resistances. Comparisons of resistances and piezo-coefficients in differing operating modes can provide a measure of mechanical stresses acting on the device.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies AG
    Inventors: Udo Ausserlechner, Mario Motz
  • Patent number: 9379115
    Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhyun Shin, Minchul Kim, Seong Soon Cho, Seungwook Chol
  • Patent number: 9320134
    Abstract: A DC-DC converter module includes a multi-layer substrate, a switching IC, and a coil. The multi-layer substrate includes component mounting electrodes provided on the top surface and an input terminal, an output terminal, and ground terminals provided on the bottom surface. The switching IC switches an input voltage and includes an input electrode, an output electrode, and a ground electrode, and is mounted on the top surface of the substrate by connecting the electrodes to the component mounting electrodes. The coil is arranged within the multi-layer substrate in a spiral shape with an axis extending in the substrate stacking direction. The bottom surface side end of the coil is connected to the input/output electrode of the switching IC.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoyoshi Hiei
  • Patent number: 9059252
    Abstract: Various methods include: forming a first set of trenches in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of trenches each expose the silicon substrate and internal sidewalls of the first oxide; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a cavity corresponding with each of the first set of trenches; and partially filling each cavity with a dielectric, leaving an air gap within each cavity connected with an air gap in an adjacent cavity.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Qizhi Liu, Steven M. Shank
  • Patent number: 9059190
    Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lyndon R. Logan, Edward J. Nowak, Robert R. Robison, Jonathan K. Winslow, II
  • Patent number: 9041148
    Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Renatas Jakushokas, Vaishnav Srinivas, Robert Won Chol Kim
  • Patent number: 9035425
    Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Chao Tsao
  • Patent number: 9030029
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: May 12, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
  • Patent number: 9006860
    Abstract: A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8963277
    Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8963283
    Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
  • Publication number: 20150041949
    Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventor: Hartmud Terletzki
  • Publication number: 20150028406
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Patent number: 8940612
    Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Kamel Benaissa
  • Patent number: 8921973
    Abstract: According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hirayu
  • Patent number: 8916436
    Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Dundulachi, Antonio Molfese
  • Patent number: 8916426
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert, Thomas A. Wallner
  • Patent number: 8901704
    Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8896087
    Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies AG
    Inventor: Hartmud Terletzki
  • Patent number: 8847349
    Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Screenivasan K. Koduri
  • Patent number: 8841747
    Abstract: A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 23, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Vassil Antonov, Vishwanath Bhat, Chris Carlson
  • Publication number: 20140264727
    Abstract: A semiconductor device includes a substrate with an active pattern, the active pattern having a first extension portion extending in a first direction substantially parallel to a top surface of the substrate, a second extension portion extending from a first end of the first extension portion in a third direction oriented obliquely to the first direction, a third extension portion extending from a second end of the first extension portion in a direction opposed to the third direction, a first projection portion protruding from the second extension portion in a direction opposed to the first direction, the first projection portion being spaced apart from the first extension portion, and a second projection portion protruding from the third extension portion in the first direction, the second projection portion being spaced apart from the first extension portion.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jea-Hyun KIM, Kyong-Seok SONG, Sung-Hee HAN
  • Patent number: 8835251
    Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: YongZhong Hu, Sung-Shan Tai
  • Patent number: 8829647
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Sandra Malhotra, Hiroyuki Ode
  • Publication number: 20140239437
    Abstract: According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi HIRAYU