Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract: The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.

Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.

Abstract: The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: A manufacturing method for the nodes of the RAM device, includes the steps as follows: forming a STI layer on a substrate to divide the substrate into several active areas; sequentially forming a first insulating layer and a hard mask layer on the substrate; etching the first insulating layer to form a first hole for exposing the STI layer and partial of the active areas; filling a conductive material in the first hole to form a conductor; forming a protective layer on the top surface of the conductor, wherein each protective layer has an opening aligning the STI layer; etching the conductor from the opening until the STI layer to form a second hole for exposing the STI layer, wherein each conductor is divided into two nodes by the second hole arranged therebetween; and forming a second insulating layer in the second hole for electrically isolating the nodes.

Abstract: A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: A pin capacitor of a semiconductor device includes a first isolation layer formed in a substrate and defining a dummy active area, a plurality of gates formed over the first isolation layer, a spacer formed at both sidewalls of each of the gates, and a plug formed over the dummy active area and in contact with the spacer. The substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit. That is, the pin capacitor includes a first capacitor including the gate, the isolation layer, and the substrate and a second capacitor including the gate, the spacer, and the plug, which are coupled in parallel to each other.

Abstract: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.

Abstract: An array substrate includes an active layer including a channel region, a gate electrode positioned corresponding to the channel region, and a gate insulating film between the active layer and the gate electrode. The gate electrode includes a transparent conductive film and an opaque conductive film, and the transparent conductive film is between the channel region and the opaque conductive film.

Abstract: A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.

Abstract: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.

Abstract: Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.

Abstract: A display device including: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the substrate and adjacent to the first semiconductor layer; a first insulation layer disposed on both the first semiconductor layer and the second semiconductor layer, the first insulation layer including a first opening forming a space between the first semiconductor layer and the second semiconductor layer; and a second insulation layer disposed on the first insulation layer and that fills the first opening.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.

Abstract: A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: Disclosed is an apparatus and method for plasma processing, which facilitates to constantly control a RF voltage supplied to a substrate supporting member by precisely detecting an inductive RF voltage induced to the substrate supporting member for a plasma, the apparatus comprising: a substrate supporting member for supporting a substrate, installed in a reaction room of a processing chamber; a RF generator for supplying a RF voltage to the substrate supporting member so as to form plasma in the reaction room; and a matching device for matching impedance of the RF voltage to be supplied to the substrate supporting member from the RF generator, wherein the matching device comprises: a matching unit for matching the impedance of RF voltage; and an inductive RF detecting unit which an inductive RF detecting voltage by removing noise frequency elements except a waveform of the RF voltage from a waveform of an inductive RF voltage induced to the substrate supporting member, and supplies the detected inductive RF

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.

Abstract: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is a polygon having at least eight edges, wherein the polygon is bilateral symmetry, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.

Abstract: In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude ?F, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.

Abstract: An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.

Abstract: A width of a region where each of the N wells is in contact with the buried P well is not more than 2 ?m. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

Abstract: A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.

Abstract: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.

Abstract: Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract: Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer.

Abstract: Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.

Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.