Abstract: A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

Abstract: In order to generate a pulsed signal with a desired active state without a great outlay on circuitry, the circuit according to the invention is characterized by a first and a second transistor (2, 3) in the integrated circuit, which are connected in series between a supply potential (UDD) and ground (GND), firstly a control pulse (A) having the predetermined duration being present at a control connection (G1) of the first transistor (2) and then a control pulse (B) being present at a control connection (G2) of the second transistor (3), with the result that, for the predetermined duration, firstly the first transistor (2) and then the second transistor (3) is turned on, and a resistor (6, 7) for the definition of the active signal state, which is connected outside the integrated circuit in parallel with one of the two transistors (2, 3) in the integrated circuit either between the supply potential (UDD) and the connecting point (4) or between ground (GND) and the connecting point (4).

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilcon film.

Abstract: A one-time programing memory element, capable of being manufactured in a 0.13 &mgr;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: There is provided a compound semiconductor device having a capacitor, to prevent a leakage current flowing between an upper electrode and a lower electrode of the capacitor via an insulating protective film. The compound semiconductor device comprises a first electrode of a capacitor formed on a compound semiconductor substrate via a first insulating film, a dielectric film of the capacitor formed on the first electrode, a second electrode of a capacitor formed on the dielectric film, a second insulating film for covering an upper surface and side surfaces of the second electrode, and an insulating protective film for covering the second insulating film, the dielectric film, the first electrode and the first insulating film, and having a hydrogen containing rate which is larger than the second insulating film.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: A multiple chip module (MCM) for use with baseband, RF, or IF applications includes a number of active circuit chips having a plurality of different functions. The active circuit chips are mounted on a substrate that is configured to provide an integrated subsystem in a single MCM package. The MCM includes a number of features that enable it to meet electrical performance, high-volume manufacturing, and low-cost requirements. The MCM may incorporate split ground planes to achieve electronic shielding and isolation, vias configured as both thermal sinks and grounding connections, and specifically configured die attach pads and exposed ground conductor pads.

Abstract: The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base polysilicon layer and a silicon oxide layer; forming an opening in these last two layers; performing a thermal anneal in an oxidizing atmosphere; depositing a silicon nitride layer and a spacer polysilicon layer; depositing an emitter polysilicon layer; and making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.

Abstract: A silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active device region and a region containing grid-like field oxide devices. The grid-like field oxide region has a plurality of field oxide layers, a plurality of first-type-ion-doped regions underneath the field oxide layers and a plurality of second-type-ion-doped region in the substrate between the various field oxide layers. A plurality of junction regions are formed between the first-type-ion-doped regions and the second-type-ion-doped regions. The junction regions impede the flow of an eddy current along a prescribed direction. A dielectric layer is formed over the substrate covering the active devices and the field oxide devices. The inductor device is formed on the dielectric layer above the field oxide devices.

Abstract: A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

Abstract: The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components (12) and passive components (16, 18, 20). The active CMOS components (12) are formed in a semiconductor substrate (10) which has a specific resistivity in the order of magnitude of k&OHgr;cm. In the semiconductor substrate (10), and under the active CMOS components (12), a buried layer (22) is formed which has a specific resistivity in the order of magnitude of &OHgr;cm. The passive components (16, 18, 20) are formed in or on a layer (14) of insulating material which is arranged on the semiconductor substrate (10). A conducting contact layer (24) is arranged on that surface of the semiconductor substrate (10) which is not facing the layer (14) of insulating material.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming exposed during subsequent processing that could otherwise remove field oxide. In one embodiment, the capped slit isolates two cells of a flash EEPROM device, and the field oxide lines the slit and serves as the tunneling oxide in the cells. In another embodiment, the slit is filled with a plug of dielectric material.

Abstract: A new method is provided for the creation of a high Q inductor. STI trenches are etched for both the active region and the inductor region. The location of the STI region for the inductor is removed from the active region by a significant distance. A thick layer of photoresist is deposited over the surface of the substrate that does not coincide with the surface of the substrate over which the inductor is to be created. A high-energy ion implant is performed after which the thick layer of photoresist is removed. The inside surfaces of the STI trenches are lined after which the STI trenches are filled and the process of creating the semiconductor device proceeds, using conventional methods of fabrication of active components and the inductor whereby the inductor is created overlying the surface of the substrate into which the high-energy ion implant has been performed.

Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

Abstract: A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.

Abstract: A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: A packaged integrated circuit configured for interconnection to an external component comprises a die (1) having a high frequency contact (8), the die (1) being disposed on a lead frame (3). The lead frame (3) comprises a plurality of leads (9). At least two of the leads are first and second RF port leads (9a, 9b) which are electrically connected to the high frequency contact (8). When mounted to a printed circuit board substrate, there is a capacitor (12) connected between the first and second RF port leads (9a, 9b) to achieve frequency specific signal attenuation at an unwanted frequency with minimal contribution of insertion loss at a desired frequency.

Abstract: A semiconductor device having multiple circuit elements capable of performing different functions and that operate at a high frequency includes island regions on which the circuit elements are located and isolation regions that surround the island regions and thus, the circuit elements. The island regions electrically separate the circuit elements from each other. A capacitor is connected between a substrate portion of the semiconductor device and ground. The isolation regions include a conductive region with a conductivity type opposite to the conductivity type of the substrate portion, such that a parasitic capacitor is formed between the substrate portion and the conductive region. The parasitic capacitor prevents signal leakage between the circuit elements and the island regions.

Abstract: An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

Abstract: In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is different from the first direction. Collectively, the first and second trenches define a plurality of different substrate elevations with adjacent elevations being joined by sidewalls which extend therebetween. Sidewall spacers are formed over the sidewalls, and material of the first layer is substantially selectively etched relative to material from which the spacers are formed. Material comprising the spacer material is substantially selectively etched relative to the first material. In a preferred implementation, the etching provides a plurality of cells which are separated from one another by no more than a lateral width dimension of a previously-formed spacer.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

Abstract: An integrable circuit inductor (220) is formed from a patterned conductive material (110) that has a major portion completely encapsulated by a material (221, 223) that is substantially electrically non-conductive, and that has a magnetic response at the operating frequency of the inductor (220). Preferably, an amorphous ferrite material is used for encapsulation, which provides a closed magnetic flux path for the inductor (220) when processing a signal at its operating frequency.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P.sup.+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P.sup.+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) exhibiting enhanced immunity to Hot Carrier Effects (HCEs), and a method by which the MOSFET may be formed. To form the MOSFET there is first provided a semiconductor substrate having a gate dielectric layer formed thereupon. The gate dielectric layer has a gate electrode formed thereupon, where the gate dielectric layer extends beyond a pair of opposite edges of the gate electrode. Formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode is a pair of low dose ion implants. Formed upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode is a pair of conductive spacers. The pair of conductive spacers partially overlaps the pair of low dose ion implants. Finally, there is formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes.

Abstract: The invention relates to a polysilicon resistor made by forming a film of polysilicon doped with an impurity on a dielectric film on a semiconductor substrate and patterning the polysilicon film. An object of the invention is to provide a polysilicon resistor which has a low resistance value and occupies a small area. A slot is formed in the dielectric film and is filled with the polysilicon film. The dielectric film and the patterned polysilicon film are overlaid with a second dielectric film, and a pair of contact windows are opened in the second dielectric film such that each contact window is partly over an end section of the slot. A plurality of parallel slots can be formed in the first dielectric film to further lower the resistance value or to further reduce the area of the patterned polysilicon film. As an alternative, at least one slot is formed in the substrate and is filled with a polysilicon film after depositing a dielectric film on the substrate surface including the surfaces in the slot(s).

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance.Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip.

Abstract: The present invention relates to a MOS capacitor. According to this invention, the MOS capacitor has a transistor structure. One electrode of the capacitor is connected to an emitter of the transistor and the other electrode of the capacitor is connected to a collector of the transistor. When the MOS capacitor is biased by static electricity the electrostatic durability is improved, since an electrostatic discharge path is formed by breakdown of a collector and an emitter.

Abstract: A high-capacitance thin film capacitc is compact and has a low profile. A dielectric layer 3 is formed between opposed electrodes 1 and 2. Between the electrodes and the dielectric layer are two layers of conductive particles, 4 and 5.

Abstract: An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A CMOS layout enables the matching of an intentionally created parasitic capacitance to an existing parasitic capacitance, for example, a gate-to-drain capacitance of a MOSFET, with a high degree of precision. This precise matching allows a differential pair of MOSFETs acting as the input of an amplfier to have intentionally created capacitances (that match the parasitic gate-to-drain capacitances) cross-coupled between the inputs and the outputs of the differential pair. This cross-coupling of matching capacitances effectively cancels the bandwidth reducing effect of the gate-to-drain capacitances of the differential pair. The layout provides for the interdigitation of the gates of the differential pair, with each input transistor comprising at least two transistors connected together to form a single input transistor.

Abstract: An integrated circuit structure including dielectric barrier layer compatible with perovskite ferroelectric materials and comprising zirconium titanium oxide, ZrTiO.sub.4, and a method of formation of the dielectric barrier layer by sol gel process is described. The amorphous, mixed oxide barrier layer has excellent dielectric properties up to GHz frequencies, and crystallizes above 800.degree. C., facilitating device processing. In particular, the barrier layer is compatible with lead containing perovskites, including PZT and PLZT ferroelectric dielectrics for example for application in non-volatile memory cells, and high value capacitors for integrated circuits, using silicon or GaAs integrated circuit technologies.

Abstract: A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.

Abstract: A termination for a high-temperature superconductive thin-film microwave device formed on the obverse side of a substrate with the reverse side of the substrate having a ground plane. The termination can include a thin-film resistor being integral with an operative component, with the substrate being a preselected dielectric substrate. The resistor can have an epitaxially-formed layer of molybdenum metal of a first preselected thickness on the obverse side, and an epitaxially-formed layer of titanium metal of a second preselected thickness thereon. The termination includes a epitaxially-formed thin-film capacitor integral with the resistor. The capacitor can have a layer of titanium metal formed on a portion of the obverse side with a layer of gold metal formed thereon. The substrate can be lanthanum aluminate, and the high-temperature superconductive film can be a yttrium-barium-copper-oxide film. The ground plane can be made of a high-temperature superconductive film and annealed gold.

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Abstract: An integrated circuit having a monolithic device such as an inductor suspended over a pit in the substrate to reduce parasitic capacitances and enhance the self-resonant frequency of the inductor.

Abstract: An insular shaped polycrystalline silicon film is formed by adhering its entire bottom face to the surface of a insulation film which is formed on the main face of a silicon substrate. A resistance element which contains designated impurities is formed in the central part of the polycrystalline silicon film. A non-doping region which essentially does not contain impurities and is adheres to all the sides of the resistance element, is positioned on the peripheral region except for the central part of the polycrystalline silicon film. By performing heat treatment when a non-doping amorphous silicon pattern is formed on the insulating film, the amorphous silicon pattern is convened to a non-doping polycrystalline silicon pattern. By using this method, a semiconductor device which has only small variances in its resistance value, which provides more efficient heat radiation, and which enables higher integration of a silicon substrate can be obtained.

Abstract: Dielectrically isolated trench fill material is used for the formation of one or more isolated resistor elements within respective ones of a plurality of dielectrically isolated island components in which circuit devices are formed, or in adjacent substrate material. A respective island may have a plurality of trench strip resistor devices, which may have the same or differing resistor values depending upon their geometries or doping concentrations. In addition, the resistor-containing architecture may include one or more conductive cross-unders each defined by a respective cross-under trench strip. A cross-under trench strip contains conductive material, such as heavily doped polysilicon, as opposed to lightly doped polysilicon of the resistor fill material.

Abstract: A semiconductor device has a substrate and a trench formed therein, the semiconductor device including a dielectric formed on the surface of the trench, a first amorphus silicon film formed on the dielectric film, a dopant film, a second amorphus silicon film, and a capping film formed between the dopant film and one of the first and second amorphus silicon films, the dopant film being formed between the other of the first and second amorphus silicon films and the capping film. The capping film is formed from one of silicon oxide and silicon nitride.

Abstract: A semiconductor integrated circuit device is provided with, in a land formed on a semiconductor substrate, a plurality of resistor layers constituted by semiconductor layers of a conductive type reverse to that of the land, and two of the plurality of the resistor layers are connected in series between a supply voltage and a reference potential. The land of the reference potential side resistor layer of the resistor layers connected in series is formed separately from the lands of the other resistor layers, and a voltage lower than a voltage applied to the other resistor layers is applied to the reference potential side resistor layer.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type formed on the semiconductor substrate; an impurity diffusion layer of the second conductivity type embedded between the semiconductor substrate and the epitaxial layer and having an impurity concentration greater than that of the epitaxial layer; a resistance region reaching the impurity diffusion layer from a surface of the epitaxial layer and extending substantially vertically to the surface of the epitaxial layer; an insulating film defining the resistance region; and a lead region selectively formed between the surface of the epitaxial layer and the impurity diffusion layer.

Abstract: A polycrystalline silicon layer 9 for a base leading electrode is formed on an element forming region divided by an element isolating layer which is formed by burying a BPSG film 8 in a groove. A depression generated on the element isolating layer is filled with a PSG film 11 which is formed as a part of an interlayer insulating film on the surface of the device including the polycrystalline silicon layer 9 by the spin-coating method so that the upper surface of the device is flattened. A polycrystalline silicon layer 13 is provided on the element isolating layer as a resistor layer so that the resistor layer is disposed between the adjacent transistors. The area of a circuit block is reduced to achieve a high integration and reduction in parasitic capacitance. This enables the high speed operation.

Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.

Abstract: A capacitor is formed in three adjacent conductive layers of a semiconductor integrated circuit chip. A first plate of the capacitor is formed in the middle layer. A second plate is formed in the upper and lower layers plus a small portion of the middle layer which interconnects the upper and lower layers and forms a U-shaped structure surrounding the first plate. These capacitors are preferably formed in pairs with the first plates interconnected. The second plates may be connected to different voltage supplies to form a capacitive voltage divider.