Abstract: A memory device with composite contact plug and method for manufacturing the same. The composite contact plug comprises a first insulating layer deposited on a semiconductor substrate. A contact hole is formed to penetrate through the first insulation layer. A barrier layer is deposited in the contact hole and fills a portion of the contact hole. A contact plug is formed on the barrier layer and fills the contact hole. The first insulating layer is etched back until the surface of the first insulating layer is below the contact plug. A diffusion barrier layer is then deposited on the first insulating layer and the contact plug. The diffusion barrier layer is planarized until the contact plug is exposed to form a composite contact plug. The memory device is constructed on the composite contact plug.

Abstract: Lanthanum oxide-based gate dielectrics are provided for integrated circuit field effect transistors. The gate dielectrics may include lanthanum oxide, preferably amorphous lanthanum oxide and/or an alloy of lanthanum oxide and silicon oxide, such as lanthanum silicate (La2SiO5). Lanthanum oxide-based gate dielectrics may be fabricated by evaporating lanthanum on a silicon surface of an integrated circuit substrate. The lanthanum may be evaporated in the presence of oxygen. Lanthanum and silicon may be co-evaporated. An anneal then may be performed. Lanthanum oxide-based dielectrics also may be used for integrated circuit capacitors.

Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.

Abstract: A SOI semiconductor device comprises a resistor body which is formed of a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film and which is dielectrically isolated by an insulating film, wherein a resistance value of the resistor body is set to be a predetermined value by the concentration of impurities contained in the top semiconductor layer and by the dimension of the resistor body.

Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.

Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.

Abstract: In one aspect, a method of interconnecting two or more foils of a capacitor, the method comprising connecting together one or more anode connection members of one or more anode foils and one or more cathode connection members of one or more cathode foils and electrically isolating the one or more anode foils from the one or more cathode foils.

Abstract: A semiconductor device has a silicon layer and a first dielectric layer. A transistor has a drain and a source that are at least partially in the silicon layer. The transistor further has a gate and a spacer defining the gate. The first dielectric layer forms the spacer. A capacitor has first and second electrodes, the first electrode is formed at least partially in the silicon layer, and the first dielectric layer provides a dielectric for the capacitor between the first and second electrodes. A resistor has a resistive region formed at least partially in the silicon layer and has first and second resistor contact areas defined by the first dielectric layer. A second dielectric layer electrically isolates the transistor, the capacitor, and the resistor from conductive lines.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region. The poly silicon region is formed having a first doped region longer than a second doped region. The poly silicon region as one single structure is adapted to function as a resistor and a diode coupled in series, said structure adapted to generate currents in a feedback loop to generate a BGR voltage. In forming the sub-1V BGR circuit, a silicide blocking mask (already available in the process flow for forming a standard semiconductor device) is used to prevent spacer oxide from forming above the center portion of the poly silicon region. In turn, silicide contacts can be formed away from the center portion of the poly silicon region.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.

Abstract: A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the cell-transistor and has the potential for increasing the node capacitance (like DRAM storage node).

Abstract: A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.

Abstract: A semiconductor device may have an insulating layer comprising a silicon oxide film or the like formed so as to cover an entire upper surface of a semiconductor substrate. A resistance element comprising MoSix is formed on the insulating layer. An insulating film is provided on the surface of the semiconductor substrate above the insulating layer. A through-hole is provided in the insulating film located above the resistance element, and an electrode provided above the insulating film is electrically connected to the resistance element through this through-hole.

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes 111.

Abstract: Thin film circuit elements including capacitors, resistors, and inductance elements are formed on a large substrate, and semiconductor chips are wire bonded to the substrate. The elements and chips are sealed by potting a sealing resin. The large substrate is divided into multiple stripe substrates by dicing and a thin-film conductive layer is sputtered on cut surfaces of the stripe substrates, thereby electrically connecting edges of lower conductive patterns to edges of upper conductive patterns exposed from side surfaces of the sealing resin through the thin-film conductive layer. A Ni foundation layer and Au layer are successively plated on a surface of the thin-film conductive layer to form edge electrodes on side surfaces of the stripe substrates and the stripe substrates are divided finely into individual alumina substrates.

Abstract: A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices.

Abstract: RF power transistor provided with an internal shunt inductor, characterized in that the shunt is produced in two separated, capacitors (Cb, Cp), each internally bonded to the transistor internal active die (AD) through internal leads (Li, Ld1), one of which capacitors (Cp) being connected to the transistor lead (L) by a further bond wire (Ld).

Abstract: A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.

Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply.

Abstract: Patterned ground planes are formed between out-of-plane microcoil structures and underlying integrated circuits (ICs). Each out-of-plane coil includes a series of loops extending from base (contact) pads formed on a dielectric layer (e.g., thick IC passivation, or BCB formed on thin passivation). Losses due to capacitive coil-to-substrate coupling are minimized using a central ground plane structure located under the base pads of the microcoil. Magnetic losses are reduced by forming a low-resistance ground plane structure including end portions located outside of the ends of the microcoil. The low-resistance ground plane can be slotted to reduce the loop size of eddy current pathways. The low-resistance ground plane is formed from one or more of the top IC metal layers, copper pads formed between the IC passivation and the dielectric, portions of the metal used to form the microcoil, or combinations thereof.

Abstract: In a semiconductor substrate, at least one diffusion region exists between resistors on an element isolation layer, and the resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Abstract: In a method for manufacturing a thin-film capacitor for performing temperature compensation by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={∈0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, ∈0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, and

Abstract: A resistor element has a ceramic body with a first outer electrode and a second outer electrode formed on its mutually opposite externally facing end surfaces and a plurality of mutually oppositely facing pairs of inner electrodes inside the ceramic body. Each of these pairs has a first inner electrode extending horizontally from the first outer electrode and a second inner electrode extending horizontally from the second outer electrode towards the first outer electrode and having a front end opposite and separated from the first inner electrode by a gap of a specified width, these plurality of pairs forming layers in a vertical direction. The gap of at least one of these plurality of pairs of inner electrodes is horizontally displaced from but overlapping with the gaps between the other pairs of inner electrodes. For producing such a resistor element, the distance of displacement is set according to a given target resistance value intended to be had by the resistor element.

Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.

Abstract: A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon “floaters,” which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses successive etches. One of these etches selectively isolates a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by photoresist.

Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in the semiconductor substrate; and a strip of second well with the second conductivity type in the semiconductor substrate. The strip of second well is located below and adjacent to the strip of first well, whereby forms a junction barrier for reducing the cross talk and the eddy current.

Abstract: Disclosed herein is a communication module, comprising a semiconductor chip in which channels for allowing signal converting means to convert current signals inputted from input terminals to voltage signals and outputting the same from output terminals respectively are arranged in parallel in plural form, and wherein the semiconductor chip is comprised principally of a semiconductor substrate in which a second semiconductor layer is provided on a first semiconductor layer with an insulating layer interposed therebetween, each of the signal converting means is formed in a channel forming region of the second semiconductor layer, which is defined for each channel, and the input and output terminals are formed on the channel forming regions of the second semiconductor layer with the insulating layer interposed therebetween.

Abstract: Within both a microelectronic fabrication and a method for fabricating the microelectronic fabrication, there is employed at least one fuse layer electrically connected with a series of patterned conductor layers separated by a series of dielectric layers, where the at least one fuse layer is formed at a level no lower than a highest of the series of patterned conductor layers within the microelectronic fabrication. When formed within the context of the foregoing constraint, there is provided enhanced access for actuation of the at least one fuse layer within the microelectronic fabrication.

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a power source voltage and a grounding voltage formed between said first P-well region and said bottom N-well region. Thus it is not necessary to maintain a device region, to form a capacitance, to form wiring or maintain a wiring region as in a conventional MOS capacitance while it is possible to obtain a required decoupling capacitance.

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

Abstract: A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor.

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: In a semiconductor device comprising first and second layer wirings formed with a space left therebetween and a capacitor formed in the space and electrically connected to the first and the second layer wirings, the capacitor comprises a via electrically connected to one of the first and the second layer wirings, an electrode made of a conductive material and electrically connected to the one of the first and the second layer wirings through the via, and a dielectric film formed between the electrode and the other of the first and the second layer wirings.

Abstract: An integrated inductive element may be formed over a substrate. A trench may be defined in a variety of shapes in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic coupling between integrated inductors associated with the same integrated circuit.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: RF power transistor provided with an internal shunt inductor, characterized in that the shunt is produced in two separated, capacities (Cb, Cp), each internally bonded to the transistor internal active die (AD) through internal leads (Li, Ld1), one of which capacities (Cp) being connected to the transistor lead (L) by a further bond wire (Ld).

Abstract: A multiple layer inductor structure in which the difference in phase current between upper and lower spiral inductor segments is reduced so as to thereby obtain not only a significant reduction in area but also a substantial increase in self-resonance frequency and a concomitant increase in the operating frequency range. The structure incorporates upper and lower spiral inductor sections, the lower section being disposed on the surface of a semiconductor substrate and the upper section being disposed on the surface of a dielectric layer which separates the respective spiral inductor sections. A plurality of electrically conductive vias interconnect adjacent concentric loop segments of the spiral inductor sections, so that as current flows through the inductor element it passes from one of the upper and the lower inductor sections to the other of the upper and lower inductor sections, alternating between these levels a number of times (i.e., a number less than or equal to the number of concentric segments).