Abstract: In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

Abstract: Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

Abstract: In a microelectronic device formed on a substrate 12, a pair of trenches 30, 36 branch at their intersection to provide branches 31-34 surrounding a sacrificial island 42. Sacrificial island 42 may comprise substrate material or other material or a void for absorbing the axial stresses propagated along the lengths of trenches 30, 36.

Abstract: A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.

Abstract: A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

Abstract: A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

Abstract: A bipolar transistor includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer having a bottom surface and side surfaces surrounded by the insulating layer. The semiconductor layer includes a collector region formed in a first surface portion of the semiconductor layer, and a collector lead region having a concentration higher than that of the collector region. The collector read region includes a silicon single crystal layer formed in a second surface portion of the semiconductor layer, and a polysilicon layer having side surfaces surrounded by the silicon single crystal layer. A base region is formed on the collector region, and an emitter region is formed in the base region.

Abstract: A biasing method for and IC with enhanced reverse bias breakdown. A field plate covering the surface PN junction and extending laterally therefrom is biased to partially deplete the island under the field plate and the substrate supporting the island is biased to complete the total depletion of the island under the field plate, establishing a substantially merged vertical field at less than critical for avalanche. Because most of the charge is required to support the vertical component of the field, the rate of change in the horizontal component is small per unit of additional terminal voltage and the lateral extension of the field plate increases the breakdown voltage beyond the plane breakdown for a PN junction of a given doping profile.

Abstract: Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: A conductivity modulation type field effect transistor comprises an n.sup.- type low concentration impurity layer of high resistance formed on an n.sup.+ type silicon substrate, a first channel region of a given width formed on the low concentration impurity layer, a pair of p type gates oppositely formed with the first channel region therebetween, an n.sup.- type low concentration impurity layer formed on the first channel region including the p.sup.+ gate, a p channel layer including two channel regions formed on the n.sup.- type low concentration impurity layer, and a pair of n.sup.+ type sources formed on the second channel region with their center aligned with a center of the first gate means, in which, after the formation of the n.sup.

Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Abstract: The trench pattern of a dielectrically isolated island architecture is filled with doped polysilicon and used as an interconnect structure for circuit devices that are supported within the islands, thereby decreasing the amount of topside interconnect and reducing the potential for parasitics beneath tracks of surface metal. The trench pattern may serve as a voltage distribution network or provide crossunders beneath surface tracks. In addition, at least one of the islands may contain one or more auxiliary poly-filled trench regions to perform the crossunder function. Such an auxiliary trench region may be also provided in an island that contains a circuit device. Manufacture of the conductor-filled trench structure may be facilitated by depositing polysilicon over a dielectrically coated trench grid structure and then planarizing the polysilicon to the surface of the oxide dielectric. The exposed polysilicon is doped and then oxidized to seal the dopant, which forms a thin oxide layer on the poly.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming a depression on a substrate, bonding a plate of a single crystal semiconductor material on the substrate to establish a contact such that a closed space is formed in the substrate in correspondence to the depression, reducing the thickness of the plate, forming a penetrating opening through the plate in communication to the space to form a bridging part in the plate as a region left from the formation of the penetrating opening, forming an insulation film to cover at least a lower major surface and both side walls of the bridging part, filling the space by depositing polysilicon through the penetrating opening, providing a conductivity to the polysilicon that fills the space, removing the polysilicon that has been deposited on the upper surface of the bridging part to expose a crystal surface of the semiconductor material forming the plate, and forming an active device on the bridging part.

Abstract: A channel stop is self-aligned with a trench sidewall of a trench-isolated semiconductor architecture, so that there is no alignment tolerance between the stop and the trench wall. An initial masking layer, through which the trench pattern is to be formed in a semiconductor island layer, is used as a doping mask for introducing a channel stop dopant into a surface portion of the semiconductor layer where the trench is to be formed. The lateral diffusion of the dopant beneath the oxide and adjacent to the trench aperture defines the eventual size of the channel stop. The semiconductor layer is then anisotropically etched to form a trench to a prescribed depth, usually intersecting the underlying semiconductor substrate. Because the etch goes through only a portion of the channel stop diffusion, leaving that portion which has laterally diffused beneath the oxide mask, the channel stop is self-aligned with the sidewall of the trench.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region.

Abstract: A dielectric isolated substrate wherein a connecting polycrystalline silicon layer has smooth and flat surface on which a single crystal support is bonded and has a densified crystal structure, or is obtained by further heat treatment at 800.degree. C. or higher after deposition, or has no orientation as to growth direction of polycrystalline silicon, or a buffering layer is formed between a polycrystalline silicon layer and a single crystal support, is excellent in bonding between the single crystal support and the polycrystalline silicon layer by preventing voids at the bonded surface, while enhancing reliability.

Abstract: A semiconductor device includes a semiconductor substrate, first and second semiconductor layers of opposite conductivity types successively disposed on the semiconductor substrate, and a via hole structure including a hole penetrating through the first and second semiconductor layers and into the substrate, the via holes being defined by a side wall of the first and second layers and of the substrate, an electrically conducting material disposed on the side wall contacting the first and second semiconductor layers, and an electrically isolating region disposed in the first and second layers at the side wall and contacting the electrically conducting material. The electrically isolating region is formed with an ion flux applied either before or after etching of the via hole.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.