Abstract: A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.

Abstract: A solid state imaging device includes: an imaging region formed in an upper part of a substrate made of silicon to have a photoelectric conversion portion, a charge accumulation region of the photoelectric conversion portion being of a first conductivity type; a device isolation region formed in at least a part of the substrate to surround the photoelectric conversion portion; and a MOS transistor formed on a part of the imaging region electrically isolated from the photoelectric conversion region by the device isolation region. The width of the device isolation region is smaller in its lower part than in its upper part, and the solid state imaging device further includes a dark current suppression region surrounding the device isolation region and being of a second conductivity type opposite to the first conductivity type.

Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Abstract: The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies.

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract: A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.

Abstract: Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation layer is to be formed. The photodiode may be formed in an active region of the semiconductor substrate, and the first conduction type impurity region may be formed in sidewalls of the trench. The first insulating layer may be formed inside the trench, and a conduction layer may be formed inside the trench and doped with second conduction type impurities. A second insulating layer may be formed inside the trench.

Abstract: A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form embedded spacers. Conventional source/drain regions may then be formed.

Abstract: Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; a well, having a well contact connection region, formed in the semiconductor substrate; a transistor formed on the well; an isolation region formed between the transistor formed on the well, and the well contact connection region; and a silicide layer formed between a bottom surface of the isolation region, and the semiconductor substrate.

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at least two epitaxially deposited layers tuning a gap between the at least two opposing faces.

Abstract: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.

Abstract: Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly depositing a seed layer on the activated non-continuous metal layer and the plurality of non-deposited regions within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free metal filled recess.

Abstract: A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Abstract: A semiconductor device provided with: a channel region formed in a surface of a semiconductor substrate in a predetermined depth range, a trench being formed in the surface as penetrating the channel region in a depthwise direction; a gate insulating film formed on an inside wall of the trench, the gate insulating film being in contact with the channel region; and a gate electrode including: a polysilicon layer opposing the channel region with the gate insulating film interposed therebetween, the polysilicon layer being embedded in an internal space of the trench at least in the predetermined depth range; and a low-resistance layer essentially formed from a metal element and disposed in the trench above the polysilicon layer that opposes the channel region.

Abstract: There is provided a method for forming wiring or an electrode by coating a substrate with a composition comprising (A) a complex of an amine compound and a hydrogenated aluminum compound and (B) a titanium compound or a composition comprising the complex and (C) metal particles and subjecting the obtained coating film to heating and/or a light treatment. By the method, a film can be formed that uses a conductive film forming composition with which wiring and an electrode that can be suitably used for electronic devices can be formed easily and inexpensively.

Abstract: Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the semiconductor wafer. The semiconductor chip separated from such a semiconductor wafer constitutes an electronic component with external contacts in the form of edge contacts. Such an electronic component of semiconductor chip size can be used in diverse ways.

Abstract: According to some embodiments, a structure of vertical transistor includes gate electrodes distanced by a predetermined interval in an active region, formed in a vertical shape to have a predetermined depth from a top surface of a semiconductor substrate. A gate insulation layer is formed between one side wall of the gate electrode and the substrate. A gate spacer is formed in another sidewall of the gate electrode, covering the gate electrode. A contact plug is formed between the gate spacer. A plug impurity layer is formed in a lower part of the contact plug, and source and drain are formed opposite to the gate electrode within the active region. Thereby, an area occupied by a gate electrode is substantially reduced, so a unit memory cell has a 4F2 structure, reducing a memory cell size, by forming a vertical-type gate electrode within an active region.

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract: A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.

Abstract: A device includes banks formed on a substrate, a conducting film formed by droplet ejection onto a predetermined pattern formation region in a groove between the banks, and a second conductive film formed by droplet ejection disposed outside the pattern formation region and electrically separated from the conductive film.

Abstract: A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

Abstract: A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench upon the polysilicon liner.

Abstract: A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating layers is made from non-doped silicate glass. The first and second poly-silicon plugs are electrically coupled to each other in a thickness direction. Preferably, both the first and second insulating layers are made from non-doped silicate glass.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section which penetrates the first insulation film, element isolation region and a buried oxide film to expose the support substrate. The method also includes creating a first source interconnect, first drain interconnect and first gate interconnect which are electrically connected to the transistors, on the second insulation film. The method also includes forming dummy interconnects which are connected with these interconnects, and are electrically connected with the support substrate via the first opening section, on the second insulation film.

Abstract: A semiconductor device is equipped with fuses each made of a conductive material vertically extended through an insulator layer employed in the semiconductor device. Holes are formed which vertically penetrate the insulator layer. Sidewalls are formed on their corresponding wall surfaces of the holes. The holes formed with the sidewalls are buried with a conductive material.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Abstract: A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through holes in the wafer. An n++ diffusion region is formed in the dicing region of a semiconductor wafer by ion implanting or diffusion. The diffusion region extends to an n++ layer formed deep in the semiconductor wafer. The width of the n++ diffusion region is made wide enough to account for the blade width of a dicer, so that an n++ diffusion region remains at the outer periphery of each of the chips divided by the dicing operation. Bump electrodes on the wafer surface electrically connect with the n++ layer deep in the semiconductor through the n++ diffusion region.

Abstract: An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P+ source region 100 and N+ source region 104 are in contact with a source electrode. Consequently, the interval 106T between the long sides of the gate electrode 106 can be set up regardless of the width of the contact opening 108.

Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.

Abstract: Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.

Abstract: According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract: A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Abstract: A semiconductor device includes a silicon oxide film (2) formed in a predetermined region on a single crystalline silicon substrate (1) and a gate dielectric film (3) as a thermal oxide film formed by performing thermal oxidation on the surface of the substrate (1) in a region adjacent to the silicon oxide film (2). A polycrystalline silicon (5) (or amorphous silicon) having an oxidized surface is formed on the border between the silicon oxide film (2) and gate dielectric film (3).