Abstract: A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

Abstract: An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.

Abstract: An electronic component has a semiconductor chip with chip contacts. The chip contacts are mechanically fixed on a wiring structure and electrically connected to the wiring structure. The wiring structure is formed as a region of a structured metal plate or as a region of a structured metal layer of a metal-clad base plate. Ideally, a panel having a number of component positions is provided for receiving a number of such an electronic component.

Abstract: A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating layer and a semiconductive material are deposited in the deep trenches. The semiconductive material is recessed below a top surface of the workpiece. Shallow trenches are formed in the workpiece between adjacent second active areas, and an insulating material is deposited in the shallow trenches and in the semiconductive material recess. The deep trenches may also be formed between an adjacent first active area and second active area. The first active areas may be high voltage devices, and the second active areas may be low voltage devices. The shallow trench isolation over the recessed semiconductive material in the deep trenches is self-aligned.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through holes in the wafer. An n++ diffusion region is formed in the dicing region of a semiconductor wafer by ion implanting or diffusion. The diffusion region extends to an n++ layer formed deep in the semiconductor wafer. The width of the n++ diffusion region is made wide enough to account for the blade width of a dicer, so that an n++ diffusion region remains at the outer periphery of each of the chips divided by the dicing operation. Bump electrodes on the wafer surface electrically connect with the n++ layer deep in the semiconductor through the n++ diffusion region.

Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.

Abstract: A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.

Abstract: A process for insulating the interior of the trenches of trench type MOSgated devices in which a capping oxide is formed over the top of the trenches to span approximately a 3 micron gap and then reflowing the oxide at 1050° C. in pure O2 to flush air out of the trenches and leaving an at least partially evacuated sealed volume in each of the trenches.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclosed. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.

Abstract: An N− type epitaxial layer is formed on a P− type silicon substrate. Trenches are created so as to penetrate N− type epitaxial layer and so as to reach to a predetermined depth of P− type silicon substrate. Thermal oxide films are formed on the sidewalls of trenches. Buried polysilicon films are formed so as to fill in trenches. Thermal oxide films are formed having an approximately constant film thickness ranging from the bottoms to the edges of the openings of trenches so as not to give stress to N− type epitaxial layers. Thereby, a semiconductor device wherein a leak current is prevented can be gained.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. A device isolation film has a shape of an insulating spacer at an interface of active regions composed of a epitaxial silicon layer in a device isolation region of a semiconductor substrate and active regions composed of a semiconductor substrate, thereby minimizing a size of the device isolation region, maximizing a size of the active regions, and achieving a high integration of the device.

Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.

Abstract: The invention includes a semiconductor construction. The construction includes a semiconductive material having a surface and an opening extending through the surface. An electrically insulative liner is along a periphery of the opening. A mass comprising one or more of silicon, germanium, metal, metal silicide and dopant is within a bottom portion of the opening, and only partially fills the opening. The mass has a top surface. An electrically insulative material is within the opening and over the top surface of the mass. The top surface of the mass is at least about 200 Angstroms beneath the surface of the semiconductive material. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.

Abstract: A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.

Abstract: A method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to the portion and heavily doped of a same first conductivity type as the substrate. A conductive plate is formed at the same time as the wall, on a layer of protection of the substrate surface, in electric contact with the peripheral region, the plate extending above said peripheral region towards the inside of the portion with respect to the wall, beyond the location above the limit between the peripheral region and the substrate.

Abstract: In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes 111.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer.

Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Abstract: A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

Abstract: Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and second lines being spaced and positioned laterally adjacent one another over the insulating layer. At least some of the laterally adjacent conductive lines may have different cross-sectional shapes in a direction perpendicular to the respective line. Alternatively, or in addition, individual second series conductive lines may be spaced from adjacent first series conductive lines a distance that is less than a minimum width of the first series lines.

Abstract: A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.

Abstract: A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: In a semiconductor device having an STI structure, a space is formed by causing a recession in an oxide film on a surface of a substrate with regard to a sidewall surface of a device isolation trench at an edge of the device isolation trench, and a Si film is formed so as to fill the trench. Further, the oxide film is removed from the surface of the substrate while leaving the Si film, and the trench is filled with an oxide film. Further, the Si film is oxidized to form an oxide film forming a part of the oxide film.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

Abstract: In a semiconductor device in which an interlayer insulating layer is formed of a low density material (porous silica etc.) and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased in comparison with other parts of the interlayer insulating layer. The densification process is conducted by the elimination of microvoids near the processed surface, for example. The densification or the microvoid elimination can be conducted by use of ammonia water, vapor of ammonia water, ammonia plasma treatment, etc. By the densification process, coating of the electrically conductive material (Cu etc.

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

Abstract: A semiconductor device comprises a first insulating film, a wiring layer and a second insulating film formed in this order on a semiconductor substrate, the second insulating film being provided with one or more through holes formed onto the wiring layer, wherein the wiring layer is electrically isolated by the first insulating film and the second insulating film at a region other than a region where the through holes are formed, and a ratio between a total of a bottom area of the through holes formed onto the wiring layer and a top surface area of the wiring layer is 1:300 to 10,000.

Abstract: A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.