Abstract: The object of the present invention is to provide a copper wiring structure in which finely processed copper wiring in a wiring structure in grooves is steadily formed with a high reliability and a method for fabricating the same, wherein an electroconductive carbon layer is formed between the copper material—a copper wiring of a wiring structure in grooves in which the copper material is buried into a wiring groove or holes formed in the organic interlayer film mainly composed of carbon—and the organic interlayer film. This electroconductive carbon layer is formed after forming wiring grooves or holes in the desired region of the organic interlayer film, by a modification of the inner wall of the wiring grooves or holes by plasma irradiation. The copper wiring of the wiring structure in grooves as described above is formed by depositing copper on the electroconductive carbon layer.

Abstract: A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate also comprises a bulk portion. Bulk semiconductor circuit structures are formed in wells in the bulk portion. The bulk circuit structures may be coupled to the SOI circuit structures.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.

Abstract: In a semiconductor device having a multilayer interconnection structure, the contact resistance of a conductive plug that connects a wiring layer and an adjacent upper wiring layer is minimized by providing an enlarged portion at the lower end of the conductive plug.

Abstract: The present invention has an object to provide a high frequency integrated device which can obtain sufficient isolation even in a high frequency region of which handling frequency exceeds gigalhertz[GHz]. In a semiconductor device having an element isolation structure obtained by trench isolation, in which an insulator fills the inside of a trench formed in a semiconductor substrate, the insulator filling the trench includes a conductive material region, and the conductive material region is grounded through coupling at high frequency. With this configuration, electromagnetic waves coupled to the conductive material inside the trench are propagated to ground, thereby preventing high-frequency interference with other regions.

Abstract: The power MOSFET has a semiconductor layer formed on a highly doped semiconductor substrate of a first conductivity type. The semiconductor layer is itself of the other conductivity type and a highly doped source zone of the other conductivity type and a highly doped drain zone of the other conductivity type are formed in the semiconductor layer. The power MOSFET also has a gate electrode. A metallically conductive connection runs between the source zone and the semiconductor substrate, so that the power MOSFET is in the form of a source-down MOSFET, and the heat can be dissipated via the semiconductor substrate or a cooling fin fitted there.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: Capacitors having defect isolation and bypass characteristics. The capacitors include a first electrode, a second electrode containing electrode segments, and a dielectric layer interposed between the first electrode and second electrode. The electrode segments of the second electrode are physically separated from other electrode segments. The capacitors further include an interconnection bus electrically coupling the electrode segments of the second electrode. Selective isolation of one or more electrode segments permits isolation and bypass of any defects identified in those electrode segments.

Abstract: A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type.

Abstract: Pch-MOS transistors to which a power supply potential is applied are respectively surrounded by first trenches, and Nch-MOS transistors to which a ground potential is applied are respectively surrounded by second trenches. The first trenches are surrounded by a third trench, and the second trenches are surrounded by a fourth trench. A silicon layer existing inside the third trench is set at the power source potential. The silicon layer existing between the third and fourth trenches are set at a floating state. Accordingly, each thickness of oxide layers filling the trenches can be reduced.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider openings, thereby improving electromigration resistance without increasing narrow line resistance. Embodiments include annealing after filling the relatively narrow openings and before filling the relatively wider openings, thereby reducing void formation in narrow lines.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: A semiconductor device of a SOI (silicon on insulator) structure includes a P-type silicon support substrate, a first insulating layer formed on the semiconductor support substrate, and an SOI layer formed on the first insulating layer. A first hole is formed to penetrate through the semiconductor layer and the first insulating layer, and a P-type polysilicon layer is filled in the first hole so that the P-type polysilicon layer is electrically connected to the semiconductor support substrate. A second insulating layer is formed on the SOI layer. A second hole is formed to penetrate through the second insulating layer in alignment with the first hole, and an aluminum electrode is formed on the second insulating layer to fill the second hole, so that the aluminum electrode is electrically connected through the P-type polysilicon layer to the silicon support substrate. Thus, the potential of the silicon support substrate can be fixed through the aluminum electrode formed on the SOI layer side.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections.

Abstract: A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor substrate; multiple conductive structures formed on the top surface of the semiconductor substrate; self-aligned conductive pads filling spaces between adjacent conductive structures and between the isolation region and the conductive structures. The method includes: forming a conductive structure on a semiconductor substrate; forming insulating sidewall spacers on the conductive structures, forming a conductive layer that fills spaces between the conductive structures and contacts the semiconductor substrate; and patterning the conductive layer.

Abstract: A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

Abstract: A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided which are novel and fully improved and are capable of lowering satisfactorily a high-frequency resistance or direct current resistance in a signal line. The semiconductor device is composed of a semiconductor substrate on which predetermined circuit devices are mounted, an insulating film formed on the substrate in a manner that it covers the circuit devices and a conductive path formed on the insulating film to electrically connect the circuit devices. A concave trench is formed in a predetermined position on the semiconductor substrate and the conductive path is formed at a bottom of the concave trench in a manner that it extends along the concave trench, with interlayer dielectrics interposed between conductive layers constituting the conductive path.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: Disclosed herein is an embedded wiring structure comprising: a first interlayer dielectric film, an etch-stop layer and a second interlayer dielectric film sequentially formed on a first wiring layer in which a second wiring layer is formed in contact with a wide wall of a via plug. Since, in this structure, the second wiring layer and the via plug are in contact with each other with a relatively large surface area, deficiencies in electrical connection are hardly generated.

Abstract: The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract: First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF4 to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: There are provided a semiconductor device which can prevent short-circuit of the contact plugs and prevent exposure of wirings to ensure sufficient reliability even if level difference is caused in device isolation regions, and a method of manufacturing the same. Device isolation regions 13 are formed on a semiconductor substrate 11 to partition the semiconductor substrate 11 into a plurality of device regions 12. Then, word lines 14 are formed on the semiconductor substrate 11, and then peripheral regions of the word lines 14 are covered with a protection film. Then, impurity diffusion regions formed in the device regions 12, and then a plug insulating film is formed on an overall upper surface of the substrate 11. Then, opening portions 18a for connecting end portions of the device regions 12 are formed in the plug insulating film.

Abstract: The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Abstract: A semiconductor device is implemented having dummy patterns arranged by designedly determining the ratio of area occupied by a protruded portion of an element formation region considering the deposited state of a buried insulating film which becomes an isolation insulating film. The ratio of area occupied by a protruded portion of a dummy pattern to a predetermined cell region is defined to be almost the same as the maximum or average value of ratios of areas occupied respectively by protruded element formation regions to a plurality of predetermined regions each including a plurality of predetermined cell regions.

Abstract: Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, 180) within the field isolation region (72, 152, 172, 182). The trenches (52, 54) are filled with a material (62) that is polished or etched to form the planar field isolation region (72, 74, 152, 172, 182) where the wide, planar field isolation regions (72, 152, 172, 182) include the mesa(s) (76, 150, 170, 180). Etching can be used or by polishing with minimal, if any, dishing occurs because the widths of the trenches (52, 54) are kept relatively narrow (usually no more than five microns wide). Mesas (180) within a wide, planar field isolation region (182) can form linguistic characters to better identify the part number or mask set of the device.

Abstract: Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent layer of silicon deposited thereon. Source and drain (S/D) terminals are formed in the silicon of the recessed portions of the shallow trench isolation insulator. In this way the S/D terminals are substantially isolated from the body, thereby substantially reducing both parasitic junction capacitance and junction leakage currents. Isolation of S/D terminals in this way also reduces the degradation of effective channel length that can otherwise occur in MOSFETs.

Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by imidizing and curing an oligomeric precursor compound comprised of a central polybenzoxazole, polybezothiazole polyamic acid ester segment end-capped at each terminus with an aryl-substituted acetylene moiety such as an ortho-bis(arylethynyl)aryl group, e.g., 3,4-bis(phenylethynly)phenyl. Integrated circuit devices, integrated circuit packaging devices, and methods of synthesis and manufacture are provided as well.

Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: An isolation structure capable of preventing deterioration of breakdown voltage of a semiconductor device is obtained. The isolation structure, positioned between first and second conductive regions formed on a major surface of a semiconductor substrate for electrically insulating the first and second conductive regions from each other, includes a first conductor formed on a position deeper than the major surface of the semiconductor substrate, an insulator positioned in a direction opposite to that of the position of the first conductive region as viewed from the first conductor and formed on a position deeper than the major surface of the semiconductor substrate and a second conductor positioned in a direction opposite to that of the position of the first conductor as viewed from the insulator and formed on a position deeper than the major surface of the semiconductor substrate.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.

Abstract: A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.

Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

Abstract: A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.

Abstract: It is an object to integrate storing functions at a high density and make it possible to perform a stable operation even at a low power supply voltage. A MOS transistor including a gate electrode and an n-type impurity region serving as a source-drain has a memory capacitor comprised by a dielectric film, a conductor, and an n-type impurity region opposing to the conductor through the dielectric film in a first trench formed in a p-type epitaxial layer beneath the gate electrode. With this structure, an area occupied by the MOS transistor and the memory capacitor can be minimized. Each unit memory cell is a two-transistor memory cell in which the drain and source of a MOS transistor supply a pair of complementary signals to a detection circuit. For this reason, a storing operation can be made reliable, and a stable operation can be realized, especially, at a low voltage.

Abstract: A structure for high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices, is disclosed. The present invention includes a semiconductor substrate and at least two dielectric regions in the substrate, one of the dielectric regions being spaced from the other of the dielectric regions by a channel region. The structure also includes at least two drift regions, each of the drift regions being adjacent to and in contact with each of the dielectric regions respectively. A gate region is formed on the substrate, wherein the gate region covers the channel region and portions of the dielectric regions. A source region adjacent to one of the dielectric region is formed, wherein the source region is spaced from the channel region by such adjacent dielectric region.

Abstract: A trench DMOS device has a gate insulating layer on the bottom and sidewalls of the trench. The upper edges of the trench have an impurity injection region and are rounded. In addition, a first conductive layer is formed on the gate insulating layer, and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer. As such the first conductive layer acts as a buffer between the gate insulating layer and the filled in second conductive layer. A method for fabricating a trench DMOS device includes the steps of forming an epitaxial layer on a semiconductor substrate. Then an impurity is injected into the epitaxial layer to form an impurity injection region. Then a trench is formed in the semiconductor substrate passing through the impurity injection region. Then a dry etching process is used to round the upper edges of the trench.

Abstract: A miniaturized contact in a semiconductor substrate is provided. The contact comprises a diffused layer formed at a surface of the substrate, an interlayer film for covering the diffused layer, a plurality of lower interconnections buried within the interlayer film, an upper interconnection disposed on the interlayer film and a contact hole passing through the interlayer film for connecting the diffused layer with the upper interconnection. The contact hole has an aperture diameter equivalent to a space interval between the lower interconnections. The contact further comprises a first buried conductor disposed only from the bottom of the contact hole to a height lower than that of the lower interconnections, a side-wall insulator disposed on a side-wall of the contact hole above the first buried conductor, and a second buried conductor disposed on the first buried conductor within the contact hole.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expense of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.