Anti-fuse Patents (Class 257/530)
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Publication number: 20080217736Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.Type: ApplicationFiled: March 7, 2007Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alberto Cestero, Byeongju Park, John M. Safran
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Publication number: 20080211060Abstract: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly.Type: ApplicationFiled: March 1, 2007Publication date: September 4, 2008Inventors: Kuang-Yeh Chang, Shing-Ren Sheu, Chung-Jen Ho
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Publication number: 20080197450Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.Type: ApplicationFiled: April 15, 2008Publication date: August 21, 2008Applicants: ACTEL CORPORATION, TEXAS TECH UNIVERSITY SYSTEMInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Patent number: 7414257Abstract: The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state for use in a configurable interconnect, comprising two separate electrodes, at least one of which being a reactive metal electrode, and a solid state electrolyte arranged between said electrodes and being capable of electrolyte isolating said electrodes to define said off-state, said electrodes and said solid state electrolyte forming a redox-system having a mini-mum voltage (“turn-on voltage”) to start a redox reaction, the redox reaction resulting in the generation of metal ions to be released into said solid state electrolyte, the metal ions being reduced to increase a metal concentration within said solid state electrolyte, wherein an increase of said metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.Type: GrantFiled: March 31, 2004Date of Patent: August 19, 2008Assignee: Infineon Technologies AGInventors: Thomas D. Happ, Thomas Roehr
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Patent number: 7410838Abstract: A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer are patterned into a first line. A dielectric layer is formed on the substrate with an opening exposing the first line. A column comprising a second diode component, a buffer layer, and an anti-fuse layer is formed in the opening. A second line is formed connecting the column on the dielectric layer running generally perpendicularly to the first line.Type: GrantFiled: April 29, 2004Date of Patent: August 12, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Kern-Huat Ang
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Patent number: 7405463Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.Type: GrantFiled: June 26, 2006Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, John D. Porter
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Patent number: 7402463Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.Type: GrantFiled: August 19, 2005Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. Fuller, Louis C. Hsu
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Patent number: 7402888Abstract: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and disposed at a position adjacent to the first input/output terminal, and a fusing part which is disposed on the semiconductor chip and connected between the first and second input/output terminals.Type: GrantFiled: September 14, 2005Date of Patent: July 22, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Shuuji Matsumoto
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Patent number: 7402855Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.Type: GrantFiled: May 6, 2005Date of Patent: July 22, 2008Assignee: Sidense Corp.Inventor: Wlodek Kurjanowicz
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Patent number: 7396699Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.Type: GrantFiled: May 9, 2006Date of Patent: July 8, 2008Assignee: Micron Technology, Inc.Inventors: Kristy A. Campbell, John T. Moore
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Publication number: 20080157271Abstract: A semiconductor device has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a wiring formed in the insulating layer and an antifuse including first and second connecting portions coupled to the wiring. The anti fuse has a space provided between the first connecting portion and the second connecting portion and insulating the first connecting portion from the second connecting portion. The first connecting portion and the second connecting portion may be coupled by a conductive material disposed in the space.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazumasa SUZUKI
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Publication number: 20080157270Abstract: The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Deok-kee Kim, Anil K. Chinthakindi, Son Van Nguyen, Kelly Malone, Byeongju Park
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Publication number: 20080157125Abstract: The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-kee Kim, Byeongju Park, John M. Safran
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Publication number: 20080144355Abstract: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.Type: ApplicationFiled: November 24, 2005Publication date: June 19, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Hans M.B. Boeve, Karen Attenborough, Godefridus A.M. Hurkx, Prabhat Agarwal, Hendrik G.A. Huizing, Michael A.A. In'T Zandt, Jan W. Slotboom
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Patent number: 7388273Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: GrantFiled: June 14, 2005Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
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Publication number: 20080128853Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.Type: ApplicationFiled: November 13, 2007Publication date: June 5, 2008Inventors: Suk-hun Choi, In-gyu Baek, Jun-young Lee, Jung-hyeon Kim, Chang-ki Hong, Yoon-ho Son
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Publication number: 20080116540Abstract: A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship. The semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a low-density forming current and/or a low voltage.Type: ApplicationFiled: May 8, 2003Publication date: May 22, 2008Inventors: Qi Wang, James Scott Ward, Jian Hu, Howard M. Branz
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Publication number: 20080089108Abstract: In one embodiment, the present invention includes an apparatus having a conductive storage medium to store information in the form of electrostatic charge. The conductive storage medium can be disposed in a non-conductive layer that is formed over a charge blocking layer, which in turn may be disposed over an electrode layer. In one embodiment, a barrier layer may be disposed over the non-conductive layer. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2006Publication date: April 17, 2008Inventors: Kyu Min, Qing Ma, Nathan R. Franklin
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Patent number: 7358590Abstract: A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying a voltage to a pair of electrodes, the state change caused by the precipitous change in volume (such as bubble generation) is generated between the pair of electrodes. Short-circuiting between a pair of electrodes is promoted by acting force based on this state change. Concretely, a bubble generating area is provided in the memory element to generate a bubble between the first conductive layer and the second conductive layer.Type: GrantFiled: March 9, 2006Date of Patent: April 15, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mikio Yukawa, Yoshinobu Asami, Ryoji Nomura
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Patent number: 7358589Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.Type: GrantFiled: August 23, 2005Date of Patent: April 15, 2008Assignee: Actel CorporationInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Publication number: 20080079113Abstract: A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.Type: ApplicationFiled: October 3, 2006Publication date: April 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. Chinthakindi, Deok-kee Kim, Chandrasekharan Kothandaraman
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Patent number: 7341892Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.Type: GrantFiled: March 7, 2006Date of Patent: March 11, 2008Assignee: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Kiyoo Itoh, Motoyasu Terao, Satoru Hanzawa, Takeshi Sakata
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Publication number: 20080042235Abstract: A semiconductor memory device for reliably inducing a breakdown in the dielectric when utilizing an antifuse to write on the dielectric film even when the process scale has become more detailed. The semiconductor memory device includes an antifuse serving as the memory node, and a current regulator connected in serial with the antifuse. The current controller is comprised of a P-type semiconductor substrate and a reverse-conduction N-type well, a diode coupled to a P+ diffusion substrate of the same conducing type as the P-type semiconductor substrate. The antifuse contains at least a structure where an electrode is formed via a dielectric film on the reverse-conducting N+ diffusion layer and the P-type semiconductor substrate. The N+ diffusion layer is connected to the N-type well of diode, and the diode regulates the current.Type: ApplicationFiled: August 15, 2007Publication date: February 21, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Noriaki Kodama
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Patent number: 7332791Abstract: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.Type: GrantFiled: September 9, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shien-Yang Wu
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Publication number: 20080036033Abstract: A one-time programmable memory. The memory has a substrate, a diffused electrode disposed on the substrate, a shallow trench isolation (STI) region formed on the substrate, a insulator formed on the STI region and the substrate, and a second electrode. The insulator separates the second electrode from the diffused electrode. At least a part of the second electrode overlaps at least a part of the STI region.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Applicant: Broadcom CorporationInventors: Akira Ito, Henry Chen
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Patent number: 7329911Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.Type: GrantFiled: February 9, 2005Date of Patent: February 12, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Yasunori Okayama
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Publication number: 20080029844Abstract: An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.Type: ApplicationFiled: August 3, 2006Publication date: February 7, 2008Inventors: James W. Adkisson, Jeffrey P. Gambino, Kirk D. Peterson, William R. Tonti
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Publication number: 20080023790Abstract: A mixed-use memory array is disclosed. In one preferred embodiment, a memory array is provided comprising a first set of memory cells operating as one-time programmable memory cells and a second set of memory cells operating as rewritable memory cells. In another preferred embodiment, a memory array is provided comprising a first set of memory cells operating as memory cells that are programmed with a forward bias and a second set of memory cells operating as memory cells that are programmed with a reverse bias.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Inventor: Roy E. Scheuerlein
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Patent number: 7323761Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.Type: GrantFiled: November 12, 2004Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Byeongju Park, Subramanian S. Iyer, Chandrasekheran Kothandaraman
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Publication number: 20080006904Abstract: A semiconductor device includes an etching protection layer to protect a metal layer in a bonding pad area when a metal fuse is etched.Type: ApplicationFiled: July 9, 2007Publication date: January 10, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Chear-Yeon MUN
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Patent number: 7312513Abstract: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal.Type: GrantFiled: July 10, 2006Date of Patent: December 25, 2007Inventor: William J. Wilcox
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Patent number: 7301216Abstract: A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.Type: GrantFiled: October 5, 2004Date of Patent: November 27, 2007Assignee: United Microelectronics Corp.Inventors: Chiu-Te Lee, Te-Yuan Wu
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Publication number: 20070267717Abstract: An insulator supporting an inner conductor within the outer conductor of a coaxial device formed from a portion of thermally conductive polymer composition with a thermal conductivity of at least 4 W/m-K. The portion is dimensioned with an outer diameter in contact with the outer conductor and a coaxial central bore supporting there through the inner conductor. Cavities may be formed in the portion for dielectric matching and or material conservation purposes. The insulator may be cost effectively fabricated via injection molding.Type: ApplicationFiled: March 22, 2007Publication date: November 22, 2007Applicant: ANDREW CORPORATIONInventor: Kendrick Van Swearingen
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Publication number: 20070262415Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.Type: ApplicationFiled: July 28, 2006Publication date: November 15, 2007Inventors: Casey Smith, Jasper S. Gibbons, Kunal R. Parekh
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Publication number: 20070241423Abstract: An integrated circuit comprises a plurality of layers including a first substrate with an on chip capacitor and a second substrate. In one embodiment, the second substrate has an on chip capacitor. The first and/or second substrate can include a sensor element, such as a magnetic sensor element.Type: ApplicationFiled: October 31, 2006Publication date: October 18, 2007Inventors: William P. Taylor, Ravi Vig
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Patent number: 7279772Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: GrantFiled: June 30, 2004Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Patent number: 7276775Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.Type: GrantFiled: December 26, 2002Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Anthony J. Dally, John Atkinson Fifield, John Jesse Higgins, Jack Allan Mandelman, William Robert Tonti, Nicholas Martin van Heel
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Patent number: 7274049Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.Type: GrantFiled: April 27, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Charles H. Dennison
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Patent number: 7272067Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.Type: GrantFiled: February 18, 2005Date of Patent: September 18, 2007Assignee: Altera CorporationInventors: Cheng H. Huang, Yowjuang Liu, Chih-Ching Shih, Hugh Sung-Ki O
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Patent number: 7269898Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: GrantFiled: October 4, 2006Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Patent number: 7262479Abstract: A fuse bank of a semiconductor memory device is provided. The fuse bank includes first and second laser fuses. The first laser fuse includes a first laser fusing region disposed in a first direction, a first connecting line region bent in a second direction, and a second connecting line region bent in a third direction. The second laser fuse includes a second laser fusing region disposed in the first direction, a third connecting line region bent in the second direction, and a fourth connecting line region bent in the third direction. The first laser fuse and the second laser fuse have a space of a predetermined distance there between. The first and second laser fusing regions form a laser fusing region of the fuse bank, and the first and second laser fuse are disposed on a plane. The fuse bank is embodied on a single layer.Type: GrantFiled: July 14, 2003Date of Patent: August 28, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Sung Seo, Hyun-Soon Jang
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Patent number: 7256471Abstract: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.Type: GrantFiled: March 31, 2005Date of Patent: August 14, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
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Patent number: 7253430Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.Type: GrantFiled: August 20, 2003Date of Patent: August 7, 2007Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, D. Mark Durcan, Brent D. Gilgen
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Patent number: 7253496Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.Type: GrantFiled: September 29, 2005Date of Patent: August 7, 2007Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, John Kizziar
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Patent number: 7245000Abstract: A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.Type: GrantFiled: October 7, 2003Date of Patent: July 17, 2007Assignee: SanDisk CorporationInventors: Michael A. Vyvoda, Manish Bhatia, James M. Cleeves, N. Johan Knall
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Patent number: 7239006Abstract: A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).Type: GrantFiled: April 14, 2004Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper
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Patent number: 7227239Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.Type: GrantFiled: September 23, 2004Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, John Atkinson Fifield, Robert J. Gauthier, Jr., William Robert Tonti
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Patent number: 7227169Abstract: Programmable surface control devices whose physical features, such as surface characteristics and mass distribution, are controlled by the presence or absence of an electrodeposition of metal and/or metal ions from a solid solution upon application of a suitable electric field.Type: GrantFiled: October 28, 2002Date of Patent: June 5, 2007Assignee: Arizona Board of RegentsInventor: Michael N. Kozicki
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Patent number: 7215002Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).Type: GrantFiled: February 4, 2005Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: John A. Fifield, Wagdi W. Abadeer, William R. Tonti
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Patent number: 7211843Abstract: The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.Type: GrantFiled: January 31, 2003Date of Patent: May 1, 2007Assignee: Broadcom CorporationInventors: Khim L. Low, Todd L. Brooks, Agnes Woo, Akira Ito